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GitHub / zfturbo/verilog-generator-of-neural-net-digit-detector-for-fpga issues and pull requests

#36 - Adding more convolution blocks and implementation

Issue - State: open - Opened by vinhxhungw84 2 months ago

#34 - Increase convolutional speed

Issue - State: open - Opened by ECEVLSIWorld almost 3 years ago

#33 - convert_image_for_testbench.py

Issue - State: closed - Opened by ECEVLSIWorld almost 3 years ago - 9 comments

#32 - Convert_image_for_testbench.py

Issue - State: closed - Opened by ECEVLSIWorld almost 3 years ago

#31 - Fix minor bugs

Pull Request - State: closed - Opened by MaKaRoIIIKa about 3 years ago

#30 - SD RAM On DE10 Fpga

Issue - State: closed - Opened by HurairaCodes over 3 years ago

#28 - Questions about the architecture of CNN

Issue - State: open - Opened by kangliyu1 over 3 years ago - 1 comment

#27 - some questions about storage data

Issue - State: open - Opened by kangliyu1 over 3 years ago - 2 comments

#26 - Some problems with reading verilog code

Issue - State: closed - Opened by kangliyu1 over 3 years ago - 4 comments

#25 - some questions about project

Issue - State: closed - Opened by kangliyu1 almost 4 years ago - 3 comments

#24 - some question about simulasion

Issue - State: closed - Opened by kangliyu1 almost 4 years ago - 1 comment

#22 - Some questions about network architecture

Issue - State: closed - Opened by kangliyu1 almost 4 years ago - 10 comments

#21 - On the simulation problem of neuroset's verilog

Issue - State: closed - Opened by kangliyu1 almost 4 years ago - 3 comments

#20 - some question about verilog/code/neuroset

Issue - State: closed - Opened by kangliyu1 almost 4 years ago - 7 comments

#19 - Timing Simulation not working

Issue - State: open - Opened by zee9999 almost 4 years ago - 3 comments

#18 - The result of testbench doesn't match with the actual result

Issue - State: closed - Opened by hithere124 over 4 years ago - 1 comment

#17 - About Testbench.v Result

Issue - State: closed - Opened by QiQi-OvO over 4 years ago - 5 comments

#16 - Terasic DE10-Lite

Issue - State: open - Opened by Bahadiirr over 4 years ago - 1 comment

#15 - add arXiv link

Pull Request - State: closed - Opened by alxndrkalinin almost 5 years ago

#14 - update paper citation

Pull Request - State: closed - Opened by alxndrkalinin almost 5 years ago

#12 - How to simulate the generated verilog

Issue - State: open - Opened by ghost over 5 years ago - 30 comments

#11 - Fix case mismatch in filename (causes compilation failure in linux).

Pull Request - State: closed - Opened by aaronferrucci about 6 years ago

#10 - modules and/or ice40 port?

Issue - State: open - Opened by peepo over 6 years ago

#9 - Quartus compilation failing

Issue - State: open - Opened by JonathanKing01 over 6 years ago - 1 comment

#8 - 改变结构

Issue - State: open - Opened by xw2333 over 6 years ago

#7 - Fixed minor errors

Pull Request - State: closed - Opened by MaKaRoIIIKa over 6 years ago

#6 - маленькие правки

Pull Request - State: closed - Opened by MaKaRoIIIKa over 6 years ago

#5 - cam_proj.out.sdc

Issue - State: open - Opened by hooper888 over 6 years ago - 4 comments

#4 - Pin Planner for FPGA

Issue - State: open - Opened by gabrielchin96 over 6 years ago - 6 comments

#3 - Different components configure

Issue - State: open - Opened by baogiadoan almost 7 years ago - 8 comments

#2 - the question of verilog code generator

Issue - State: open - Opened by xw2333 about 7 years ago - 21 comments

#1 - How to run those python Codes to generate verilog codes step by step?

Issue - State: open - Opened by pualdelis over 7 years ago - 5 comments