Ecosyste.ms: Issues

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GitHub / kevinpt/hdlparse issues and pull requests

#27 - Update index.rst

Pull Request - State: open - Opened by skyySea1 7 months ago

#26 - Adding Bluespec Support

Issue - State: closed - Opened by iamkarthikbk about 1 year ago - 1 comment

#25 - Python3 packaging

Pull Request - State: closed - Opened by Liambeguin over 1 year ago

#24 - Need Python 3 version of this library. No longer builds due to lack of use_2to3

Issue - State: open - Opened by Anutrix about 2 years ago - 2 comments

#23 - Error in parsing the last Output

Issue - State: open - Opened by Eyantra698Sumanto over 2 years ago

#22 - doc: use BuildTheDocs, add CI workflow

Pull Request - State: closed - Opened by umarcor over 3 years ago - 1 comment

#21 - Does not look to be actively maintained

Issue - State: open - Opened by michael-etzkorn over 3 years ago - 14 comments

#20 - Documentation bug `extract_objects_from_source`

Issue - State: open - Opened by michael-etzkorn over 3 years ago

#19 - Add end markers for package and architecture

Pull Request - State: open - Opened by andresmanelli over 3 years ago - 1 comment

#18 - Add VhdlParameterType class to support vector and array parameter types

Pull Request - State: open - Opened by KatCe over 3 years ago

#16 - Parsing "output logic" port is wrong

Issue - State: open - Opened by masics almost 5 years ago

#15 - Add support for logic type and fix minor syntax error

Pull Request - State: open - Opened by hanhha almost 5 years ago

#14 - Add entity parsing

Pull Request - State: open - Opened by andresmanelli over 5 years ago - 4 comments

#13 - matching end of entity and end of architecture

Issue - State: open - Opened by m-tosch almost 6 years ago - 1 comment

#12 - Verilog and VHDL parser issues

Issue - State: open - Opened by nvzach over 6 years ago

#11 - verilog parser - parse as a port of a function's port.

Issue - State: open - Opened by KyleJeong over 6 years ago

#10 - verilog parser - Wrong parsing of comment

Issue - State: open - Opened by KyleJeong over 6 years ago

#7 - Get hdlparse registered at awesome-vhdl

Issue - State: open - Opened by Paebbels almost 7 years ago

#6 - hdl parse not working for parsing an entity

Issue - State: open - Opened by obruendl almost 7 years ago - 1 comment

#5 - Support for Verilog 2001 attributes?

Issue - State: open - Opened by mithro almost 7 years ago - 1 comment

#4 - fail to match named "end component" syntax

Issue - State: closed - Opened by bergnoli almost 7 years ago - 1 comment

#3 - cooperation

Issue - State: closed - Opened by Nic30 about 7 years ago - 1 comment

#2 - Constants not getting fetched by the parser

Issue - State: closed - Opened by mohit162009 over 7 years ago - 1 comment

#1 - No documentation

Issue - State: closed - Opened by RasmusB over 7 years ago - 1 comment