Ecosyste.ms: Issues

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GitHub / enjoy-digital/litex issues and pull requests

#2088 - video console

Issue - State: closed - Opened by uglyoldbob 5 months ago - 2 comments
Labels: answered-waiting-feedback

#2087 - build: efinix: allow clk inverting and different in clk on reg tristates

Pull Request - State: open - Opened by maass-hamburg 5 months ago - 2 comments

#2086 - build: io: don't use mutable object as default value

Pull Request - State: closed - Opened by maass-hamburg 5 months ago - 1 comment

#2085 - RFC: Etherbone address detection

Issue - State: open - Opened by m-byte 5 months ago - 2 comments

#2084 - Simulate SoC and communicate through UART

Issue - State: open - Opened by Leopard777 5 months ago - 3 comments

#2083 - build: efinix: EfinixTristateImpl: use GPIO Bus

Pull Request - State: closed - Opened by maass-hamburg 5 months ago - 1 comment

#2082 - Efinix iface signal names.

Pull Request - State: closed - Opened by enjoy-digital 5 months ago

#2081 - build: efinix: common.py; add `SDRInput`

Pull Request - State: closed - Opened by maass-hamburg 5 months ago - 4 comments

#2080 - No package metadata was found for litex

Issue - State: closed - Opened by pcotret 5 months ago

#2079 - build: efinix: ifacewriter: some fixes

Pull Request - State: closed - Opened by maass-hamburg 5 months ago - 1 comment

#2078 - build: efinix: add function to add ip

Pull Request - State: closed - Opened by maass-hamburg 5 months ago - 1 comment

#2077 - build: io.py: add QDR input, output and tristate

Pull Request - State: open - Opened by maass-hamburg 5 months ago

#2074 - build: io.py: DDRTristate: check oe2

Pull Request - State: open - Opened by maass-hamburg 5 months ago

#2073 - litex_setup: use current version of migen

Pull Request - State: open - Opened by maass-hamburg 5 months ago

#2070 - BIOS: Add BOOTP support

Pull Request - State: open - Opened by m-byte 5 months ago - 4 comments

#2068 - build: io: make oe2 of DDRTristate optional

Pull Request - State: closed - Opened by maass-hamburg 5 months ago - 6 comments

#2047 - Mode based bus crossbar

Pull Request - State: open - Opened by jdavidberger 6 months ago

#2026 - core: i2c: add i2c master

Pull Request - State: closed - Opened by maass-hamburg 7 months ago - 14 comments

#2022 - litex/tools: Add RemoteI2C

Pull Request - State: open - Opened by AndrewD 7 months ago

#2019 - add crt0.o to BIOS target list

Pull Request - State: open - Opened by hhe07 7 months ago

#2008 - Error When Trying to Measure Time in C Language

Issue - State: closed - Opened by fzhwenzhou 8 months ago - 2 comments
Labels: answered-waiting-feedback

#1990 - Initial MIPS CPUs support

Pull Request - State: open - Opened by FlyGoat 8 months ago - 7 comments

#1989 - Fix AXI version of the Zynq7000 busses and add mapped connect fuction

Pull Request - State: open - Opened by JoyBed 8 months ago - 4 comments
Labels: answered-waiting-feedback

#1975 - DTS target integration

Pull Request - State: open - Opened by AndrewD 9 months ago - 7 comments

#1965 - ulx3s ecp5 soc not working when using Lattice Diamond

Issue - State: open - Opened by dwalton65 9 months ago - 18 comments

#1959 - Add dynamic mux for UARTBone / normal UART

Pull Request - State: open - Opened by jwise 9 months ago

#1944 - When part skipped do not threat it as sent

Pull Request - State: open - Opened by nrndda 10 months ago

#1943 - Fix false path clock constraints

Pull Request - State: open - Opened by nrndda 10 months ago

#1942 - Target hooks

Pull Request - State: open - Opened by AndrewD 10 months ago - 4 comments

#1935 - Trying to interact with UART via Rust binary (stuck at liftoff)

Issue - State: open - Opened by roby2014 10 months ago - 6 comments
Labels: question, third-party-bug, answered-waiting-feedback

#1928 - Add bios disassembly file generation rules.

Pull Request - State: open - Opened by nrndda 10 months ago

#1921 - CSR ordering support in generated files

Pull Request - State: open - Opened by AndrewD 11 months ago - 4 comments

#1915 - soc/integration: Ensure the video framebuffer fits in main RAM

Pull Request - State: open - Opened by davidar 11 months ago - 1 comment

#1913 - Auto format constants in decimal or hex

Pull Request - State: open - Opened by AndrewD 11 months ago - 1 comment

#1898 - Add support for custom attributes on Signals

Pull Request - State: open - Opened by pftbest 12 months ago

#1845 - patch litex soc gen

Pull Request - State: open - Opened by jwfaye over 1 year ago

#1806 - Test litex-boards targets

Pull Request - State: open - Opened by AndrewD over 1 year ago - 2 comments

#1791 - Update gcc installation instruction

Pull Request - State: open - Opened by lianakoleva over 1 year ago

#1790 - [enh] generate SVD CSR enumeratedValue based on fields values

Pull Request - State: open - Opened by chmousset over 1 year ago - 4 comments

#1775 - gen/genlib/misc: Add CE option to WaitTimer

Pull Request - State: open - Opened by rowanG077 over 1 year ago

#1773 - issue when boot on tang-primer-20k

Issue - State: closed - Opened by Jurisu25 over 1 year ago - 3 comments

#1772 - NameError: name 'Signal' is not defined

Issue - State: closed - Opened by SunLee7 over 1 year ago - 10 comments

#1759 - Builder enhancements

Pull Request - State: open - Opened by AndrewD over 1 year ago - 2 comments

#1757 - litex/gen/sim: add Tristate special override

Pull Request - State: open - Opened by AndrewD over 1 year ago

#1750 - Various Issues with Sipeed Tang Primer 20k

Issue - State: open - Opened by bacintom over 1 year ago - 40 comments
Labels: enhancement, help-welcome :), bug?

#1740 - Add documentation arguments to builder

Pull Request - State: open - Opened by bayi over 1 year ago - 2 comments

#1735 - Adding a weak isr handler to handle non uart interrupts

Pull Request - State: open - Opened by riktw over 1 year ago - 1 comment

#1659 - csr: add ability to express clusters

Pull Request - State: open - Opened by dalegaard almost 2 years ago - 2 comments
Labels: enhancement, new-feature

#1641 - feature: Support renaming default uart to uart0.

Pull Request - State: open - Opened by jorislee almost 2 years ago - 1 comment
Labels: enhancement

#1634 - litex_ok.py bitstream configuration example

Pull Request - State: open - Opened by AEW2015 almost 2 years ago - 3 comments
Labels: new-feature

#1586 - Add I2S example code and function to add an I2S peripheral in soc.py

Pull Request - State: open - Opened by fritzbauer about 2 years ago - 1 comment

#1539 - FIX #1530: add explicit `.re` for axi-lite busses

Pull Request - State: open - Opened by bunnie about 2 years ago - 1 comment

#1528 - Pretty print Verilog constants by intelligently chosing decimal or hex

Pull Request - State: open - Opened by jevinskie about 2 years ago - 1 comment

#1522 - interconnect/axi: map from one address space to another

Pull Request - State: open - Opened by mkuhn99 about 2 years ago - 2 comments

#1513 - FIX: fix wishbone arbiter

Pull Request - State: open - Opened by bunnie over 2 years ago - 5 comments
Labels: gateware-bug, needs-review

#1510 - FIX: Handle un-aligned edge case on AXI upconverter

Pull Request - State: open - Opened by bunnie over 2 years ago - 7 comments
Labels: gateware-bug, needs-review

#1506 - RFC: Fix sensitivity dependencies in FSM for AXI-lite/AXI

Pull Request - State: open - Opened by bunnie over 2 years ago - 9 comments
Labels: enhancement, needs-review

#1473 - [WIP] Add CSR metadata generation

Pull Request - State: open - Opened by staticfloat over 2 years ago - 5 comments
Labels: enhancement, needs-review

#1430 - Axi_lite_to_wishbone: Reduce latency, make latency configurable

Pull Request - State: open - Opened by cklarhorst over 2 years ago - 12 comments
Labels: enhancement, needs-review

#1414 - ci: run on ubuntu-22.04 and cleanup

Pull Request - State: open - Opened by umarcor over 2 years ago - 2 comments
Labels: enhancement, interesting-but-needs-rework

#1336 - Extend FSM class

Pull Request - State: open - Opened by fjullien over 2 years ago

#1322 - software/common.mak: Disable _FORTIFY_SOURCE

Pull Request - State: open - Opened by zeldin over 2 years ago

#1318 - Add litex.gen.fhdl.verilog.VerilogTime to emit $time

Pull Request - State: open - Opened by jevinskie over 2 years ago

#1315 - liteeth: Add DMA interface

Pull Request - State: open - Opened by sergpolkin over 2 years ago - 2 comments
Labels: needs-review

#1314 - Couldn't Install LiteX When Using Arch Linux

Issue - State: closed - Opened by minexo79 over 2 years ago - 2 comments

#1310 - ClockFrequency() to get/set the frequency of a domain or signal

Pull Request - State: open - Opened by jevinskie over 2 years ago - 1 comment

#1308 - Add get_signals function (w/ optional recursion) for litescope usage

Pull Request - State: open - Opened by jevinskie almost 3 years ago - 1 comment

#1286 - cores/video: new VideoTextGrid component

Pull Request - State: open - Opened by swetland almost 3 years ago - 5 comments

#1283 - Etherbone testing

Pull Request - State: open - Opened by michael-betz almost 3 years ago

#1278 - Added init_array support for vexriscv to allow static C++ ctors and C…

Pull Request - State: open - Opened by DaveBerkeley almost 3 years ago - 1 comment

#1255 - Vivado IP packaging

Pull Request - State: open - Opened by sebo83910 almost 3 years ago - 3 comments
Labels: new-feature

#1235 - Add sigma-delta DAC LiteX core.

Pull Request - State: open - Opened by tcal-x almost 3 years ago - 10 comments
Labels: new-feature, needs-review

#1218 - Version control with JSON file

Pull Request - State: open - Opened by kaolpr almost 3 years ago - 12 comments
Labels: new-feature

#978 - Make bios respond to pings

Pull Request - State: open - Opened by michael-betz over 3 years ago - 1 comment
Labels: needs-review

#926 - RFC: Power optimization: multiple gated clocks

Pull Request - State: open - Opened by bunnie over 3 years ago - 1 comment
Labels: needs-review

#899 - software/bios: Add option to obtain IP address from DHCP server

Pull Request - State: open - Opened by Meet909 almost 4 years ago - 3 comments
Labels: needs-review

#777 - soc/integration/export: Add CSR aliases for devices with suffix zero

Pull Request - State: open - Opened by geertu about 4 years ago - 2 comments
Labels: interesting-but-needs-rework

#683 - Improve the performance of EtherBone bridge

Issue - State: closed - Opened by jedrzejboczar over 4 years ago - 6 comments
Labels: enhancement, question

#100 - lattice/programmer: Use --program-image option with tinyprog if addre…

Pull Request - State: closed - Opened by cr1901 over 6 years ago - 1 comment

#100 - lattice/programmer: Use --program-image option with tinyprog if addre…

Pull Request - State: closed - Opened by cr1901 over 6 years ago - 1 comment

#98 - fix typo and unused include

Pull Request - State: closed - Opened by jfng over 6 years ago - 1 comment

#98 - fix typo and unused include

Pull Request - State: closed - Opened by jfng over 6 years ago - 1 comment

#97 - minerva.core package not found

Issue - State: closed - Opened by bunnie over 6 years ago - 1 comment

#97 - minerva.core package not found

Issue - State: closed - Opened by bunnie over 6 years ago - 1 comment

#96 - build/platforms: Add TinyFPGA BX board and programmer.

Pull Request - State: closed - Opened by cr1901 over 6 years ago

#96 - build/platforms: Add TinyFPGA BX board and programmer.

Pull Request - State: closed - Opened by cr1901 over 6 years ago

#94 - lattice/icestorm: Add nextpnr pnr as alternate pnr tool.

Pull Request - State: closed - Opened by cr1901 over 6 years ago - 1 comment

#94 - lattice/icestorm: Add nextpnr pnr as alternate pnr tool.

Pull Request - State: closed - Opened by cr1901 over 6 years ago - 1 comment

#93 - Fix URL for liteUSB

Pull Request - State: closed - Opened by phlipped over 6 years ago

#93 - Fix URL for liteUSB

Pull Request - State: closed - Opened by phlipped over 6 years ago

#92 - software/bios: Gate flush_l2_cache() if L2 Cache isn't present.

Pull Request - State: closed - Opened by cr1901 over 6 years ago - 1 comment