Ecosyste.ms: Issues

An open API service for providing issue and pull request metadata for open source projects.

GitHub / zachjs/sv2v issues and pull requests

#303 - doesn't understand [a]array[b] references to array items

Issue - State: closed - Opened by pbreuer about 2 months ago - 1 comment

#302 - doesn't deal with for loops with multiple initializations

Issue - State: open - Opened by pbreuer about 2 months ago

#301 - generates wrong sized initializations on its own generated localparams

Issue - State: open - Opened by pbreuer about 2 months ago - 2 comments

#300 - Doesn't preserve comments

Issue - State: open - Opened by pbreuer 2 months ago - 1 comment

#299 - too many bindings specified for parameter overrides in instance

Issue - State: open - Opened by pbreuer 2 months ago - 7 comments

#298 - Constant function under generate

Issue - State: open - Opened by mole99 3 months ago - 2 comments

#297 - Parsing error

Issue - State: closed - Opened by miquelt9 3 months ago - 2 comments

#296 - Problem with localparam in package

Issue - State: closed - Opened by fsiegle 3 months ago - 6 comments

#295 - Improperly-handled inout ports

Issue - State: open - Opened by ldoolitt 3 months ago - 3 comments

#294 - Breakage caused by attributes

Issue - State: closed - Opened by ldoolitt 4 months ago - 6 comments

#293 - Generate _sv2v_0 problem

Issue - State: closed - Opened by BoChen-Ye 4 months ago - 4 comments

#292 - add enum attributes to enum values

Issue - State: open - Opened by rroohhh 4 months ago - 2 comments

#291 - bit fill literal '0 does not expand (sv2v) properly

Issue - State: closed - Opened by ljmalone123 5 months ago - 2 comments

#290 - Missing "wire" keyword

Issue - State: closed - Opened by ldoolitt 7 months ago - 2 comments

#289 - Assert Property ```disable iff``` not fully converted to Verilog

Issue - State: closed - Opened by HakamAtassi 7 months ago - 4 comments

#288 - [Feature Request] Copy comments over

Issue - State: closed - Opened by Willyarma 8 months ago - 4 comments

#286 - Integration with SVase?!

Issue - State: open - Opened by chili-chips-ba 8 months ago - 6 comments

#285 - SV2V QA test suite

Issue - State: closed - Opened by chili-chips-ba 8 months ago - 6 comments

#284 - Build fails on MacOS

Issue - State: closed - Opened by zaun 10 months ago - 2 comments

#283 - How to build on GNU/Linux on arm64?

Issue - State: closed - Opened by spth 10 months ago - 16 comments

#282 - How to build on GNU/Linux on ppc64?

Issue - State: closed - Opened by spth 10 months ago - 9 comments

#281 - Test correct and incorrect type parameters from CVA6

Pull Request - State: open - Opened by jrrk2 10 months ago - 3 comments

#280 - regarding system verilog to verilog

Issue - State: open - Opened by sundeep2249 10 months ago - 8 comments

#279 - File name too long

Issue - State: closed - Opened by RHamalainen 11 months ago - 3 comments

#278 - Add support for `disable` statement

Issue - State: open - Opened by spth 12 months ago - 4 comments

#277 - LLVM dependency

Issue - State: closed - Opened by jrrk2 about 1 year ago - 4 comments

#276 - Initial support for system tasks

Pull Request - State: closed - Opened by sifferman about 1 year ago - 8 comments

#275 - Automatic Function Produces Construct with Infinite Loop in Yosys

Issue - State: open - Opened by wrs225 about 1 year ago - 6 comments

#274 - Added `full_case` and `parallel_case` attributes

Pull Request - State: closed - Opened by sifferman about 1 year ago - 7 comments

#273 - Convert severity tasks to Verilog

Issue - State: closed - Opened by sifferman about 1 year ago - 3 comments

#272 - Token '#' issue in wire definition and assignment

Issue - State: closed - Opened by stitchlibar about 1 year ago - 1 comment

#270 - Support for `unique` and `priority`

Issue - State: closed - Opened by sifferman about 1 year ago

#269 - Option to Convert Procedural Blocks to Modules

Issue - State: closed - Opened by sifferman about 1 year ago

#268 - SV2V automatically removes parentheses in operator precedence

Issue - State: closed - Opened by anhdv2000 about 1 year ago - 6 comments

#267 - Width extension converts string to int and changes endianess / byte order

Issue - State: closed - Opened by vogelpi about 1 year ago - 2 comments

#266 - Converted Verilog Outputs Different Result Compared to Original SysVerilog

Issue - State: closed - Opened by marchuang6272 about 1 year ago - 3 comments

#265 - Different types in generate branches results in error

Issue - State: open - Opened by mole99 about 1 year ago - 3 comments

#264 - fork-join with wait produce a parse error

Issue - State: closed - Opened by gggmmm about 1 year ago - 2 comments

#263 - Would you please implement those enum methods for SystemVerilog ?

Issue - State: open - Opened by forthyen over 1 year ago - 1 comment

#262 - Streaming operator is not converted when combined with conditional operator

Issue - State: closed - Opened by KatCe over 1 year ago - 2 comments

#261 - `input reg` is not allowed in Verilog

Issue - State: closed - Opened by YikeZhou over 1 year ago - 2 comments

#260 - Array literals flow into Verilog unchanged

Issue - State: open - Opened by YikeZhou over 1 year ago

#259 - data type `string` not removed from module item

Issue - State: closed - Opened by YikeZhou over 1 year ago - 4 comments

#258 - Unexpected interface mismatch error when using "modport"

Issue - State: closed - Opened by YikeZhou over 1 year ago - 2 comments

#257 - package import declaration not work?

Issue - State: closed - Opened by YikeZhou over 1 year ago - 3 comments

#256 - Issue with $clog2 of a parameter

Issue - State: closed - Opened by flaviens over 1 year ago - 3 comments

#255 - name conflict

Issue - State: closed - Opened by forthyen over 1 year ago - 4 comments

#254 - 'parameter type' refers to wrong type

Issue - State: closed - Opened by elementary-particle over 1 year ago - 3 comments

#252 - False incompatible bus size error on output and reg

Issue - State: closed - Opened by stitchlibar over 1 year ago - 9 comments

#251 - using interface arrays generates broken code

Issue - State: closed - Opened by tinebp over 1 year ago - 13 comments

#250 - ifndef and define behavior not compatible with Verilog

Issue - State: closed - Opened by stitchlibar over 1 year ago - 5 comments

#249 - sv2v: unexpected non-var or non-port function decl

Issue - State: closed - Opened by gadfort over 1 year ago - 2 comments

#247 - Issues with newest iverilog

Issue - State: closed - Opened by dwRchyngqxs over 1 year ago - 3 comments

#246 - Struct parameters in module definition

Issue - State: closed - Opened by lpawelcz over 1 year ago - 6 comments

#244 - Print blocked statement to avoid dangling else even when it would be parsed correctly

Pull Request - State: closed - Opened by dwRchyngqxs over 1 year ago - 2 comments

#243 - Feature request: Documentation for contributing and writing tests

Issue - State: closed - Opened by dwRchyngqxs over 1 year ago - 1 comment

#242 - newest iverilog crashes when running tests

Issue - State: closed - Opened by dwRchyngqxs over 1 year ago - 4 comments

#241 - Make test prints a lot of warnings

Issue - State: closed - Opened by dwRchyngqxs over 1 year ago - 2 comments

#240 - Problems building

Issue - State: closed - Opened by philn128 over 1 year ago - 3 comments

#239 - Generate region standard compliance fixes

Pull Request - State: open - Opened by dwRchyngqxs over 1 year ago - 6 comments

#238 - Fixing a bug where always_* are not converted when attributed

Pull Request - State: closed - Opened by dwRchyngqxs over 1 year ago - 3 comments

#237 - Reworked attributes support

Pull Request - State: closed - Opened by dwRchyngqxs almost 2 years ago - 8 comments

#236 - Attributes in expressions

Issue - State: closed - Opened by dwRchyngqxs almost 2 years ago - 2 comments

#235 - Issue with hierarchical cast not accepted by Yosys

Issue - State: closed - Opened by flaviens almost 2 years ago - 4 comments

#234 - Missing empty port connection in output file

Issue - State: closed - Opened by Risto97 almost 2 years ago - 2 comments

#233 - interface to verilog, package files, typedef and enums

Issue - State: closed - Opened by armstrong0 almost 2 years ago - 5 comments

#232 - problem with the transaltion of ibex

Issue - State: closed - Opened by ourspalois almost 2 years ago - 3 comments

#231 - Issue in how block comments are handled

Issue - State: closed - Opened by mole99 almost 2 years ago - 2 comments

#230 - expanded interface instance

Issue - State: open - Opened by michael-lehn almost 2 years ago - 3 comments

#229 - Convertion unsized single-bit value

Issue - State: closed - Opened by kele14x almost 2 years ago - 4 comments

#228 - Could you test it ?

Issue - State: closed - Opened by forthyen about 2 years ago - 2 comments

#226 - Issue when converting CV32E40X

Issue - State: closed - Opened by mole99 about 2 years ago - 9 comments

#225 - Why converted module's name has '~' character ?

Issue - State: closed - Opened by forthyen about 2 years ago - 1 comment

#224 - data type `string` not removed from parameter

Issue - State: closed - Opened by patrickrst about 2 years ago - 2 comments

#223 - Can't resolve function name

Issue - State: closed - Opened by flaviens over 2 years ago - 2 comments

#222 - Unknown bindings port connections

Issue - State: closed - Opened by hello-eternity over 2 years ago - 2 comments

#221 - nknown bindings port connections

Issue - State: closed - Opened by hello-eternity over 2 years ago

#220 - sv2v hangs and eventually OOM

Issue - State: closed - Opened by flaviens over 2 years ago - 4 comments

#219 - Array manipulation methods

Issue - State: open - Opened by daglem over 2 years ago - 1 comment

#218 - Name of modules that contain parameterized types

Issue - State: closed - Opened by kauser-rl over 2 years ago - 27 comments

#217 - Pre-built files, how to use?

Issue - State: closed - Opened by alirazavihaeri over 2 years ago - 2 comments

#216 - Cannot read verilog code with property statements in yosys after sv2v

Issue - State: closed - Opened by mmxsrup over 2 years ago - 5 comments

#215 - Can you create a new stable release version please?

Issue - State: closed - Opened by kauser-rl over 2 years ago - 1 comment

#214 - Don't support sequence

Issue - State: closed - Opened by hello-eternity over 2 years ago - 4 comments

#213 - Modport binding fails for interface instances with same name as a type

Issue - State: closed - Opened by dsdve over 2 years ago - 5 comments

#211 - fail to make

Issue - State: closed - Opened by hello-eternity over 2 years ago - 3 comments

#210 - Judgmental Equivalence

Issue - State: closed - Opened by hello-eternity over 2 years ago - 2 comments

#209 - Parse error: missing expected `endfunction`

Issue - State: closed - Opened by hello-eternity over 2 years ago - 3 comments

#208 - Problem with sv2v executable file

Issue - State: closed - Opened by MohamedAliYounis over 2 years ago

#207 - signed to unsigned conversion in struct members causes trouble with >>>

Issue - State: closed - Opened by siquus over 2 years ago - 2 comments

#205 - Generated verilog code cannot be read by yosys

Issue - State: closed - Opened by mmxsrup almost 3 years ago - 2 comments

#204 - Extra semicolon emitted

Issue - State: closed - Opened by jiegec almost 3 years ago - 3 comments