yupferris/kaze issues and pull requests

#40 - Modules with different clock domains?

Issue - State: closed - Opened by Boscop over 1 year ago - 3 comments

#39 - test trace_test_module_2 failed: panicked at 'assertion failed: `(left == right)`

Issue - State: open - Opened by Boscop over 1 year ago - 1 comment

#38 - In-process simulator backend

Issue - State: open - Opened by yupferris almost 3 years ago

#37 - Additional trace formats

Issue - State: open - Opened by yupferris about 3 years ago

#36 - Formal verification support

Issue - State: open - Opened by yupferris about 3 years ago

#35 - Add `lsb` and `msb` convenience methods for `Signal`s

Issue - State: open - Opened by yupferris about 3 years ago

#34 - Explore async/await for co-sim threads

Issue - State: open - Opened by yupferris about 3 years ago

#33 - TraceValue

Issue - State: open - Opened by jonay2000 over 3 years ago

#32 - generate if and else ifs with macros

Pull Request - State: closed - Opened by jonay2000 over 3 years ago - 1 comment

#31 - Add continuous integration

Pull Request - State: open - Opened by jonay2000 over 3 years ago

#30 - Possible logic errors: Mutable key types

Issue - State: open - Opened by jonay2000 over 3 years ago - 1 comment

#29 - Same name for instances, memories and registers

Pull Request - State: open - Opened by jonay2000 over 3 years ago

#28 - Same name (the simple cases)

Pull Request - State: open - Opened by jonay2000 over 3 years ago

#27 - Cannot reproduce: Validation error if a module has no inputs/outputs

Issue - State: open - Opened by jonay2000 over 3 years ago - 1 comment

#26 - Best way to support IP blocks?

Issue - State: closed - Opened by MarkSwanson over 3 years ago - 4 comments

#25 - Write verilog::generate() output to a file

Issue - State: closed - Opened by Uzaaft over 3 years ago - 3 comments

#24 - Bit selection of vector signal was missing in generated verilog codes.

Issue - State: closed - Opened by ar90n over 3 years ago - 1 comment

#23 - Consider redesigning how `Module` (hierarchies) work

Issue - State: open - Opened by yupferris almost 4 years ago - 10 comments

#22 - Consider multiple clock domains

Issue - State: open - Opened by yupferris almost 4 years ago

#21 - Tracing improvements

Issue - State: open - Opened by yupferris almost 4 years ago - 2 comments

#20 - Complete add/sub overloads

Issue - State: open - Opened by yupferris almost 4 years ago

#19 - Consider growing stacks in compiler instead of iterative lowering

Issue - State: open - Opened by yupferris almost 4 years ago - 1 comment

#18 - Consider dedicated structure construct

Issue - State: open - Opened by yupferris almost 4 years ago

#17 - Consider dedicated FSM construct

Issue - State: open - Opened by yupferris almost 4 years ago

#16 - match/switch construct

Issue - State: open - Opened by yupferris almost 4 years ago

#15 - Update doc links

Issue - State: closed - Opened by yupferris about 4 years ago

#14 - Consider writing book/tutorial

Issue - State: open - Opened by yupferris about 4 years ago - 6 comments