Ecosyste.ms: Issues
An open API service for providing issue and pull request metadata for open source projects.
GitHub / yosyshq/yosys-bench issues and pull requests
#23 - add some small examples where yosys has worse results than vivado
Pull Request -
State: open - Opened by nakengelhardt almost 5 years ago
#23 - add some small examples where yosys has worse results than vivado
Pull Request -
State: open - Opened by nakengelhardt almost 5 years ago
#22 - Add a number of DSP Verilog benchmarks
Pull Request -
State: closed - Opened by eddiehung about 5 years ago
#22 - Add a number of DSP Verilog benchmarks
Pull Request -
State: closed - Opened by eddiehung about 5 years ago
#21 - [Draft] Automate Benchmark flow
Pull Request -
State: open - Opened by dh73 about 5 years ago
- 2 comments
#21 - [Draft] Automate Benchmark flow
Pull Request -
State: open - Opened by dh73 about 5 years ago
- 2 comments
#20 - [Review] SystemVerilog benchmarks (posit cores, Hermes-Lite2 RF design) . Verilog bft-flow benchmark.
Pull Request -
State: open - Opened by dh73 about 5 years ago
#20 - [Review] SystemVerilog benchmarks (posit cores, Hermes-Lite2 RF design) . Verilog bft-flow benchmark.
Pull Request -
State: open - Opened by dh73 about 5 years ago
#19 - Fixing VHDL benchmarks
Pull Request -
State: open - Opened by dh73 over 5 years ago
#19 - Fixing VHDL benchmarks
Pull Request -
State: open - Opened by dh73 over 5 years ago
#18 - Add T2 core and BOOM
Pull Request -
State: closed - Opened by daveshah1 over 5 years ago
#18 - Add T2 core and BOOM
Pull Request -
State: closed - Opened by daveshah1 over 5 years ago
#17 - Add Verilog CAM
Pull Request -
State: closed - Opened by eddiehung over 5 years ago
#17 - Add Verilog CAM
Pull Request -
State: closed - Opened by eddiehung over 5 years ago
#16 - More CI: try running small/large (now with -noflatten) in separate tasks
Pull Request -
State: closed - Opened by eddiehung over 5 years ago
#15 - Add verilog-ethernet benchmark from @alexforencich
Pull Request -
State: closed - Opened by eddiehung over 5 years ago
#15 - Add verilog-ethernet benchmark from @alexforencich
Pull Request -
State: closed - Opened by eddiehung over 5 years ago
#14 - Add yosys-sanity.sh that just reads in source and does hierarchy check
Pull Request -
State: closed - Opened by eddiehung over 5 years ago
#14 - Add yosys-sanity.sh that just reads in source and does hierarchy check
Pull Request -
State: closed - Opened by eddiehung over 5 years ago
#13 - Add two large mux-heavy Verilog benchmarks
Pull Request -
State: closed - Opened by eddiehung over 5 years ago
#13 - Add two large mux-heavy Verilog benchmarks
Pull Request -
State: closed - Opened by eddiehung over 5 years ago
#12 - Add supporting files for mux benchmark
Pull Request -
State: closed - Opened by eddiehung over 5 years ago
#12 - Add supporting files for mux benchmark
Pull Request -
State: closed - Opened by eddiehung over 5 years ago
#11 - Add benchmarks/small/mux generator
Pull Request -
State: closed - Opened by eddiehung over 5 years ago
#10 - Cirrus ci
Pull Request -
State: closed - Opened by trcwm over 5 years ago
#10 - Cirrus ci
Pull Request -
State: closed - Opened by trcwm over 5 years ago
#9 - Initial MARLANN
Pull Request -
State: closed - Opened by eddiehung over 5 years ago
#9 - Initial MARLANN
Pull Request -
State: closed - Opened by eddiehung over 5 years ago
#8 - Added support for config.json configurations
Pull Request -
State: closed - Opened by trcwm over 5 years ago
#8 - Added support for config.json configurations
Pull Request -
State: closed - Opened by trcwm over 5 years ago
#7 - Initial selection of dspfilters from @ZipCPU
Pull Request -
State: closed - Opened by eddiehung over 5 years ago
- 1 comment
#7 - Initial selection of dspfilters from @ZipCPU
Pull Request -
State: closed - Opened by eddiehung over 5 years ago
- 1 comment
#6 - Add 3-168 bit LFSR benchmark, add yosys-ice40-flopcount
Pull Request -
State: closed - Opened by eddiehung over 5 years ago
#5 - Add picorv32 v1.0 to verilog/benchmarks_large
Pull Request -
State: closed - Opened by eddiehung over 5 years ago
#4 - Added READMEs to the verilog benchmarks
Pull Request -
State: closed - Opened by trcwm over 5 years ago
#3 - Renamed readme
Pull Request -
State: closed - Opened by trcwm over 5 years ago
#2 - Add description for each of the benchmarks
Issue -
State: closed - Opened by mithro over 5 years ago
- 1 comment
#1 - Fix cwd for calling subprocess
Pull Request -
State: closed - Opened by eddiehung almost 6 years ago