ymherklotz/verismith issues and pull requests

#104 - iverilog emulates the syn_vivado.v command generated by vivado

Issue - State: open - Opened by FSY369 about 2 months ago

#103 - It would be nice to have a stack.yaml in the repo?

Issue - State: closed - Opened by bojle 5 months ago - 10 comments

#102 - Small style changes and add mutation infrastructure + bug fix

Pull Request - State: open - Opened by dwRchyngqxs 6 months ago

#101 - Add explicit imports to fix build issues

Pull Request - State: closed - Opened by flaviens 7 months ago - 4 comments

#100 - Add flake.nix support.

Pull Request - State: closed - Opened by RCoeurjoly 9 months ago - 2 comments

#99 - Build failed due to dependency errors (tasty-hedgehog >=1.0 && <1.2)

Issue - State: closed - Opened by YikeZhou 11 months ago - 1 comment

#98 - nix build failure on Ubuntu 20.04.6 LTS (GNU/Linux 5.15.90.1-microsoft-standard-WSL2 x86_64)

Issue - State: closed - Opened by blackcoatzhou about 1 year ago - 1 comment

#97 - Export configuration for invalid generation

Pull Request - State: closed - Opened by dwRchyngqxs about 1 year ago

#96 - Update the nixpkgs pin to include vector 0.13

Issue - State: closed - Opened by ymherklotz about 1 year ago

#95 - can I use the EMI？

Issue - State: closed - Opened by 1353369570 over 1 year ago - 1 comment

#94 - verismith never generates simple 'if' statements - only 'if/else' statements

Issue - State: open - Opened by yurivict almost 2 years ago
Labels: enhancement

#93 - Implement strict parsing of config file

Pull Request - State: closed - Opened by ymherklotz almost 2 years ago

#92 - Remove Travis CI file and possibly add Github Actions

Issue - State: closed - Opened by ymherklotz almost 2 years ago
Labels: bug

#91 - Verilog2005 Support

Pull Request - State: closed - Opened by dwRchyngqxs almost 2 years ago - 3 comments

#90 - verismith generates mismatching Verilog assign statements

Issue - State: open - Opened by yurivict almost 2 years ago
Labels: bug

#89 - verismith doesn't generate assign statements with concatenation and bit selectors in the LHS

Issue - State: open - Opened by yurivict almost 2 years ago
Labels: enhancement

#88 - verismith doesn't complain about undefined config values in config file

Issue - State: closed - Opened by yurivict almost 2 years ago - 1 comment
Labels: enhancement

#87 - The README section 'Build with cabal from source' should begin with 'cabal update'

Issue - State: closed - Opened by yurivict about 2 years ago

#86 - Fix build issue due to the outdated 'time' module

Pull Request - State: open - Opened by yurivict about 2 years ago - 7 comments

#85 - Build fails: 'can't find include file HsTimeConfig.h' and other errors

Issue - State: closed - Opened by yurivict about 2 years ago - 6 comments

#84 - Bump dependencies to compile with GHC 9.2

Pull Request - State: closed - Opened by mpardalos about 2 years ago

#83 - Fixed invalid AST when parsing >=

Pull Request - State: closed - Opened by dwRchyngqxs about 2 years ago

#82 - Added equivalence checking after shuffling

Pull Request - State: closed - Opened by dwRchyngqxs about 2 years ago

#81 - Shuffle signal and module instantiation

Issue - State: open - Opened by dwRchyngqxs about 2 years ago
Labels: bug

#80 - Exposing equivalence check to CLI

Pull Request - State: closed - Opened by dwRchyngqxs about 2 years ago

#79 - I can't understand the readme you wrote

Issue - State: closed - Opened by cemery123 almost 3 years ago - 19 comments

#78 - "Resources" links are broken

Issue - State: closed - Opened by forrestv almost 4 years ago - 1 comment

#77 - Add SystemVerilog parsers found in sv-tests?

Issue - State: open - Opened by mithro over 4 years ago - 2 comments
Labels: enhancement

#76 - Better reducer and formatting

Pull Request - State: closed - Opened by ymherklotz almost 5 years ago

#75 - Add distance function

Pull Request - State: closed - Opened by ymherklotz almost 5 years ago

#74 - Add gitignore for experiments

Pull Request - State: closed - Opened by RCoeurjoly almost 5 years ago - 1 comment

#73 - Ignore dist, which is created when running cabal run verismith

Pull Request - State: closed - Opened by RCoeurjoly almost 5 years ago

#72 - License has contradictory wording

Issue - State: closed - Opened by krupan almost 5 years ago - 3 comments

#71 - run nix-build has no response

Issue - State: closed - Opened by semiwizard almost 5 years ago - 1 comment

#70 - Upgrading packages to work with 8.8.2

Pull Request - State: closed - Opened by ymherklotz almost 5 years ago

#69 - cabal: Could not resolve dependencies:

Issue - State: closed - Opened by semiwizard almost 5 years ago - 3 comments

#68 - Parallelise the reduction algorithm

Issue - State: closed - Opened by ymherklotz over 5 years ago
Labels: maybe

#67 - Remove DRBG dependency

Pull Request - State: closed - Opened by ymherklotz over 5 years ago

#66 - Division with context-sensitive guards

Issue - State: closed - Opened by ymherklotz over 5 years ago
Labels: enhancement

#65 - Fix parser with new modules

Issue - State: closed - Opened by ymherklotz over 5 years ago - 1 comment
Labels: bug

#64 - Error in for loop reduction

Issue - State: closed - Opened by ymherklotz over 5 years ago - 1 comment
Labels: bug

#63 - Update dependency for Hedgehog

Issue - State: closed - Opened by ymherklotz over 5 years ago
Labels: bug

#62 - Add simple nondeterminism to the generation step

Issue - State: closed - Opened by ymherklotz over 5 years ago
Labels: enhancement

#61 - Support combinational always blocks

Issue - State: closed - Opened by ymherklotz over 5 years ago
Labels: enhancement

#60 - Add reduction algorithm optimisation

Issue - State: closed - Opened by ymherklotz over 5 years ago - 1 comment
Labels: enhancement

#59 - Add support for more Verilog constructs

Issue - State: closed - Opened by ymherklotz over 5 years ago
Labels: enhancement

#58 - Mask the output of simulator based on golden design

Issue - State: closed - Opened by ymherklotz over 5 years ago - 1 comment
Labels: bug

#57 - Add a rerun option instead of hijacking reduce

Issue - State: closed - Opened by ymherklotz over 5 years ago - 1 comment
Labels: maybe

#56 - Add python scripts into the main program

Issue - State: closed - Opened by ymherklotz over 5 years ago
Labels: enhancement

#55 - Add option to remove folders that pass synthesis

Issue - State: closed - Opened by ymherklotz over 5 years ago
Labels: enhancement

#54 - Not all inputs get initialised in module

Issue - State: closed - Opened by ymherklotz over 5 years ago

#53 - [WIP] Fix for modport

Pull Request - State: closed - Opened by ymherklotz almost 6 years ago

#52 - Fix resizing of module inputs and outputs

Issue - State: closed - Opened by ymherklotz almost 6 years ago - 1 comment

#51 - Remove unsafe head from Lenses

Issue - State: closed - Opened by ymherklotz almost 6 years ago
Labels: maybe

#50 - Make findActiveWire work with SourceInfo

Issue - State: closed - Opened by ymherklotz almost 6 years ago - 1 comment

#49 - Add LDPE module to vivado cells

Issue - State: closed - Opened by ymherklotz almost 6 years ago

#48 - Add simulator options to config.toml

Issue - State: closed - Opened by ymherklotz almost 6 years ago

#47 - Think about removing the Arbitrary module

Issue - State: closed - Opened by ymherklotz almost 6 years ago

#46 - Change the hierarchy of AST

Issue - State: closed - Opened by ymherklotz almost 6 years ago

#45 - Add documentation to all functions

Issue - State: closed - Opened by ymherklotz almost 6 years ago

#44 - Extend parser to accept all Verilog

Issue - State: closed - Opened by ymherklotz almost 6 years ago - 1 comment

#43 - Add Report type to generate reports from

Issue - State: closed - Opened by ymherklotz almost 6 years ago - 1 comment

#42 - Add support for Covered

Issue - State: closed - Opened by ymherklotz almost 6 years ago
Labels: wontfix

#41 - Implement some EMI approaches

Issue - State: closed - Opened by ymherklotz almost 6 years ago
Labels: wontfix

#40 - Add single seed to runs, so that these can be rerun

Issue - State: closed - Opened by ymherklotz almost 6 years ago

#39 - Remove quickcheck completely

Issue - State: closed - Opened by ymherklotz almost 6 years ago - 1 comment

#38 - Parser not identifying input and output

Issue - State: closed - Opened by ymherklotz almost 6 years ago

#37 - Support multiple modules and way to specify top module

Issue - State: closed - Opened by ymherklotz almost 6 years ago

#36 - Make types in AST more efficient

Issue - State: closed - Opened by ymherklotz almost 6 years ago

#35 - Add test case reducer

Issue - State: closed - Opened by ymherklotz almost 6 years ago

#34 - Add method to count nodes in the AST

Issue - State: closed - Opened by ymherklotz almost 6 years ago