GitHub / wallento/riscv-python-model issues and pull requests
#9 - CSR instructions should treat immediate as unsigned
Issue -
State: open - Opened by MichaelBell about 2 years ago
#8 - Fix right shifts and sltu[i] instructions
Pull Request -
State: open - Opened by Kristopher38 over 3 years ago
#7 - Instruction SLTU in insn.py still using the old "def execute(self, State)" interface
Issue -
State: open - Opened by mbrandalero almost 5 years ago
#6 - Add little-endian/big-endian bytes extraction for Register
Pull Request -
State: closed - Opened by rswarbrick over 5 years ago
- 1 comment
#5 - Fix encoding for J-type instructions
Pull Request -
State: closed - Opened by rswarbrick over 5 years ago
- 2 comments
#4 - Fix import of TerminateException in sim.py
Pull Request -
State: closed - Opened by rswarbrick over 5 years ago
- 2 comments
#3 - Fixes for SRL and SRA
Pull Request -
State: closed - Opened by rswarbrick over 5 years ago
- 2 comments
#2 - Improving privileged instruction support
Pull Request -
State: closed - Opened by ghost over 5 years ago
- 2 comments
#1 - Adding support for RV32A atomic operations (AMO*, LR, and SC)
Pull Request -
State: closed - Opened by ghost over 5 years ago
- 3 comments