umd-memsys/DRAMsim3 issues and pull requests

#44 - Does DRAMsim3 support DMA?

Issue - State: open - Opened by Z-KN about 1 year ago

#43 - [bug] dead lock in Controller::ScheduleTransaction

Issue - State: open - Opened by gxflying over 1 year ago - 2 comments

#42 - Feature/func

Pull Request - State: open - Opened by gkstnwls0 over 1 year ago

#41 - why we discard the PRECHARGE cmd here?

Issue - State: open - Opened by gxflying over 1 year ago

#40 - Dev

Pull Request - State: open - Opened by gkstnwls0 over 1 year ago

#39 - is there any papers/results/diagrams to show the differences between the simulation result and the verilog model results?

Issue - State: open - Opened by gxflying over 1 year ago

#38 - fix the infinity loop bug encountered in the R->W dependency

Pull Request - State: open - Opened by LauXy over 1 year ago

#37 - where to find the DRAM block size

Issue - State: open - Opened by 770958 over 1 year ago

#36 - HBM1 Bandwidth

Issue - State: closed - Opened by NicolasMeseguer over 1 year ago - 1 comment

#35 - Size of each transaction

Issue - State: open - Opened by kaustubhcs over 1 year ago - 1 comment

#34 - Running gem5 with DRAMsim3

Issue - State: open - Opened by tanglt1514 almost 2 years ago

#33 - Hi, how can I use CMD_TRACE feature?

Issue - State: open - Opened by TurnOffNOD almost 2 years ago

#32 - SST Integration Link is broken in README

Issue - State: open - Opened by kaustubhcs about 2 years ago

#31 - size of configs files

Issue - State: open - Opened by gieflij about 2 years ago - 1 comment

#30 - Edit README.md and .gitignore

Pull Request - State: closed - Opened by ljw8161 about 2 years ago

#29 - Insert a space between value and inline comment in config files

Issue - State: open - Opened by smosanu over 2 years ago

#28 - Verilog Validation

Issue - State: closed - Opened by Yicheng22 over 2 years ago - 3 comments

#27 - Got a confusing issue, maybe it's a corner case when scheduling transaction

Issue - State: open - Opened by TQLyu over 2 years ago

#26 - fix index increment

Pull Request - State: open - Opened by mjtsai almost 3 years ago

#25 - Zsim integration

Issue - State: open - Opened by moonkyung almost 3 years ago

#24 - `tRFCb` is not applied for `BANK_LEVEL_STAGGERED` refresh policy

Issue - State: open - Opened by channoh about 3 years ago

#23 - Add build testing

Pull Request - State: closed - Opened by sudhanshu2 about 3 years ago

#22 - How to use DRAMsim3 with gem5

Issue - State: closed - Opened by Jeongmiu about 3 years ago

#21 - DRAMSim3 LPDDR4 to DRAMSim2

Issue - State: open - Opened by btwbtw01 about 3 years ago

#20 - Run simulation until the end of trace file

Issue - State: open - Opened by smosanu about 3 years ago - 1 comment

#19 - Broken Link to SST Integration Info

Issue - State: open - Opened by plavin about 3 years ago

#18 - Power and Energy

Issue - State: open - Opened by hanm2019 about 3 years ago

#17 - DDR5 Support

Issue - State: open - Opened by pjattke over 3 years ago

#16 - [thermal] power_epoch_period vs [other] epoch_period

Issue - State: open - Opened by gkothar1 over 3 years ago

#15 - A problem:TypeError: init() takes exactly 1 argument (2 given)

Issue - State: open - Opened by PeterLiudong over 3 years ago

#14 - Config files for larger than 8GB of DDR4

Issue - State: open - Opened by mewais over 3 years ago

#13 - fix some typos and outdated paths

Pull Request - State: closed - Opened by HaFred over 3 years ago

#12 - trace_gen.py dramsim2 gen traces looks different

Issue - State: closed - Opened by HaFred over 3 years ago - 2 comments

#11 - Write drain fix

Pull Request - State: closed - Opened by tommydcjung over 3 years ago

#10 - Multi-channel LPDDR4

Issue - State: open - Opened by dpriver over 3 years ago

#9 - a question with command ./build/dramsim3main configs/DDR4_8Gb_x8_3200.ini -c 100000 -t sample_trace.txt

Issue - State: closed - Opened by langrange-L almost 4 years ago - 1 comment

#8 - ‘class dramsim3::MemorySystem’ has no member named ‘GetChannelMask’ when building zsim with dramsim3

Issue - State: closed - Opened by my569 about 4 years ago - 2 comments

#7 - Missing RankBackgroundEnergy function (DTHERMAL=1) leads to fail compiling

Issue - State: closed - Opened by mchlmrz about 4 years ago - 5 comments

#6 - Multiple trace file

Issue - State: closed - Opened by avacoder42 about 4 years ago - 4 comments

#5 - Flushing submitted transactions when working with a CPU simulator

Issue - State: closed - Opened by gkothar1 over 4 years ago

#4 - HBM controller bug

Issue - State: closed - Opened by albertsegura over 4 years ago - 1 comment

#3 - HBM Configs

Issue - State: open - Opened by pfotouhi over 4 years ago

#2 - Scheduling commands

Issue - State: open - Opened by taehyunzzz over 4 years ago

#1 - Measuring queuing latency

Issue - State: open - Opened by pfotouhi over 4 years ago

GitHub / umd-memsys/DRAMsim3 issues and pull requests