Ecosyste.ms: Issues

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GitHub / ultraembedded/biriscv issues and pull requests

#27 - Develop

Pull Request - State: open - Opened by joaopedrobuzattim 2 months ago

#26 - SDK environment

Issue - State: open - Opened by chengquan 4 months ago - 4 comments

#26 - SDK environment

Issue - State: open - Opened by chengquan 4 months ago - 4 comments

#24 - Wrong opcode for CSR_MCYCLE, CSR_MTIME and CSR_MTIMEH

Issue - State: open - Opened by Gianluke27 over 1 year ago

#24 - Wrong opcode for CSR_MCYCLE, CSR_MTIME and CSR_MTIMEH

Issue - State: open - Opened by Gianluke27 over 1 year ago

#23 - FPGA Implementation

Issue - State: open - Opened by SB308 over 1 year ago

#23 - FPGA Implementation

Issue - State: open - Opened by SB308 over 1 year ago

#21 - Division by 0

Issue - State: open - Opened by CrazybinaryLi almost 2 years ago

#21 - Division by 0

Issue - State: open - Opened by CrazybinaryLi almost 2 years ago

#20 - make failed...error

Issue - State: open - Opened by crayon7442 almost 2 years ago - 1 comment

#20 - make failed...error

Issue - State: open - Opened by crayon7442 almost 2 years ago - 1 comment

#19 - Operating Frequency

Issue - State: open - Opened by anandmay22 over 2 years ago - 1 comment

#19 - Operating Frequency

Issue - State: open - Opened by anandmay22 over 2 years ago - 1 comment

#17 - Consider adding biriscv to LiteX CPU ecosystem?

Issue - State: open - Opened by mithro almost 3 years ago

#17 - Consider adding biriscv to LiteX CPU ecosystem?

Issue - State: open - Opened by mithro almost 3 years ago

#16 - LWGP

Issue - State: open - Opened by altuSemi about 3 years ago

#16 - LWGP

Issue - State: open - Opened by altuSemi about 3 years ago

#15 - about Branch target buffer

Issue - State: open - Opened by cool-ic over 3 years ago - 2 comments

#15 - about Branch target buffer

Issue - State: open - Opened by cool-ic over 3 years ago - 2 comments

#14 - Linux compatibility

Issue - State: closed - Opened by JOHNTBIJU over 3 years ago - 1 comment

#13 - link library for biriscv

Issue - State: open - Opened by riya1407 over 3 years ago

#13 - link library for biriscv

Issue - State: open - Opened by riya1407 over 3 years ago

#12 - JTAG Debugging Request

Issue - State: open - Opened by nvitya over 3 years ago

#12 - JTAG Debugging Request

Issue - State: open - Opened by nvitya over 3 years ago

#11 - Benchmark scores

Issue - State: closed - Opened by kuopinghsu over 3 years ago - 6 comments

#11 - Benchmark scores

Issue - State: closed - Opened by kuopinghsu over 3 years ago - 6 comments

#10 - Not an issue, rather a request

Issue - State: open - Opened by bhawandeepsingh almost 4 years ago

#9 - How initializa the memory from the verilog

Issue - State: open - Opened by emiliofmc7 over 4 years ago

#8 - TCL file for FPGA build

Issue - State: open - Opened by alaasal over 4 years ago - 1 comment

#7 - Questions Biriscv

Issue - State: open - Opened by emiliofmc7 over 4 years ago

#6 - enable write to MTIME

Pull Request - State: closed - Opened by altuSemi over 4 years ago

#5 - DEBUG interface

Issue - State: closed - Opened by zhuzhizhan over 4 years ago - 2 comments
Labels: enhancement

#4 - Using own ELF results in an infinite loop

Issue - State: open - Opened by MakisChristou over 4 years ago - 5 comments

#3 - How to use my own test programs?

Issue - State: closed - Opened by hyf6661669 almost 5 years ago - 2 comments

#1 - Bug: 'csr_swap' type operations on SATP register do not work

Issue - State: open - Opened by ultraembedded almost 5 years ago
Labels: bug