Ecosyste.ms: Issues

An open API service for providing issue and pull request metadata for open source projects.

GitHub / ucb-bar/chisel2-deprecated issues and pull requests

#750 - ccccccglcttvtcigucglvlrgbihthbuurcfiiicudnlj

Issue - State: closed - Opened by albert-magyar almost 6 years ago - 2 comments

#749 - Issue deprecation warning on startup.

Pull Request - State: closed - Opened by ucbjrl almost 7 years ago - 6 comments

#748 - Attaching Analog(X.W) to several Analog(1.W)

Issue - State: closed - Opened by mwachs5 almost 7 years ago - 1 comment

#747 - Is it legal to connect empty bundles?

Issue - State: closed - Opened by mwachs5 about 7 years ago - 1 comment

#746 - Update README - more prominent notice of migration to Chisel3.

Pull Request - State: closed - Opened by ucbjrl about 7 years ago

#745 - documentation link is dead

Issue - State: closed - Opened by PeterAaser over 7 years ago - 12 comments

#744 - Move chisel3 compatible casts {as,to}{S,U}Int from Bits to Node.

Pull Request - State: closed - Opened by ucbjrl almost 8 years ago

#743 - Updatedeprecated

Pull Request - State: closed - Opened by ucbjrl almost 8 years ago

#742 - verilator fails to compile small Example

Issue - State: open - Opened by oharboe almost 8 years ago

#741 - Wide rom fix

Pull Request - State: closed - Opened by ucbjrl almost 8 years ago

#740 - unable to create a ROM with datawidth more than 64

Issue - State: closed - Opened by anupkini almost 8 years ago - 1 comment

#739 - libraryDependencies latest.release not found

Issue - State: closed - Opened by colin4124 about 8 years ago - 2 comments

#738 - C++ output from Chisel has been dropped

Pull Request - State: open - Opened by olofk over 8 years ago - 1 comment

#737 - Queue is not getting synthesized

Issue - State: open - Opened by preyas3359 over 8 years ago

#736 - Buildinfo

Pull Request - State: closed - Opened by ucbjrl over 8 years ago

#735 - Use unconventional (but consistent) package name.

Pull Request - State: closed - Opened by ucbjrl over 8 years ago

#734 - Add support for Chisel3 tutorial (organization + features)

Pull Request - State: closed - Opened by ucbjrl over 8 years ago

#733 - Invalid verilog generated with constant idx into ROM

Pull Request - State: open - Opened by da-steve101 over 8 years ago - 1 comment

#732 - Invalid verilog generated with constant idx into ROM

Pull Request - State: closed - Opened by da-steve101 over 8 years ago - 1 comment

#731 - Allow specifying of clock for blackbox module

Pull Request - State: open - Opened by da-steve101 over 8 years ago - 2 comments

#729 - Exception: sbt.TrapExitSecurityException

Issue - State: open - Opened by drom over 8 years ago - 2 comments

#728 - Add support for new chisel3 tutorials.

Pull Request - State: closed - Opened by ucbjrl over 8 years ago

#727 - Support bulk connects in `when`?

Issue - State: open - Opened by jkorinth over 8 years ago

#726 - Uninferrable width on reg after using fromBits

Issue - State: open - Opened by da-steve101 over 8 years ago

#725 - Q: "make getting-started" fails

Issue - State: closed - Opened by omerfirmak over 8 years ago - 3 comments

#724 - RegUpdate and RegReset?

Issue - State: open - Opened by cornytrace over 8 years ago - 3 comments

#721 - Remove extraneous apply() from vec.tabulate - #718

Pull Request - State: closed - Opened by ucbjrl over 8 years ago

#720 - Add Chisel3 clock methods.

Pull Request - State: closed - Opened by ucbjrl over 8 years ago

#719 - Fill(Chisel.UInt, Int) is in Chisel2, but not supported by Chisel3

Issue - State: closed - Opened by ucbjrl over 8 years ago - 1 comment

#718 - Vec.fill appears to be badly broken

Issue - State: closed - Opened by ascenium over 8 years ago - 10 comments

#717 - fix the outputlist size

Pull Request - State: open - Opened by songmaotian over 8 years ago - 3 comments

#715 - Will OrderedDecoupledHWIOTester insert bubble for the output.ready signal?

Issue - State: open - Opened by songmaotian over 8 years ago - 2 comments

#714 - Renameiotesters

Pull Request - State: closed - Opened by ucbjrl over 8 years ago

#713 - val differs from expression after assignment

Issue - State: open - Opened by pw-gecos over 8 years ago

#712 - Return Seq, not Vec, from PriorityEncoderOH

Pull Request - State: closed - Opened by aswaterman over 8 years ago

#711 - Use Seq, not Iterable, when order matters

Pull Request - State: closed - Opened by aswaterman over 8 years ago

#710 - Chisel3 compatibility: Allow asserts with empty messages

Pull Request - State: closed - Opened by aswaterman over 8 years ago

#709 - Verilog doesn't use`else` so memory not inferred as RAM

Issue - State: open - Opened by sclukey over 8 years ago - 2 comments

#708 - Update to current sbt resolver idiom.

Pull Request - State: closed - Opened by ucbjrl over 8 years ago

#707 - Cautionary Tale -- Chisel/ISE issue

Issue - State: open - Opened by shunshou over 8 years ago - 3 comments

#706 - Inconsistent member names in C++ emulator

Issue - State: open - Opened by kenmcmil over 8 years ago

#705 - Chisel3compatibilitycheck

Pull Request - State: closed - Opened by ucbjrl over 8 years ago - 1 comment

#704 - add package object with new literal creation implicits

Pull Request - State: closed - Opened by chick over 8 years ago

#702 - Flag to enable warnings for any modules with any unconnected ports

Issue - State: open - Opened by ascenium over 8 years ago - 1 comment

#700 - Chisel3compatibilitycheck

Pull Request - State: closed - Opened by ucbjrl almost 9 years ago

#699 - Bulk connects do not override bundle components

Issue - State: open - Opened by colinschmidt almost 9 years ago - 4 comments

#698 - Migrated black box to separate file

Pull Request - State: closed - Opened by da-steve101 almost 9 years ago - 2 comments

#697 - Catting a UInt of width 0 leads to strange sim results

Issue - State: open - Opened by da-steve101 almost 9 years ago - 1 comment

#696 - Compilation Error when assigning from other clock

Issue - State: open - Opened by da-steve101 almost 9 years ago - 4 comments

#695 - Correct signature for vcd dump methods (lacked t and reset arguments).

Pull Request - State: closed - Opened by ucbjrl almost 9 years ago

#694 - (Relevant to Enum:) Uppercase identifiers assumed to be stable identifiers in extractor/unapply context

Issue - State: open - Opened by sdtwigg almost 9 years ago
Labels: Documentation, Syntax

#693 - Improve log2* functions, as with Chisel3

Pull Request - State: closed - Opened by aswaterman almost 9 years ago

#692 - Testers Vec size issue: java.lang.IndexOutOfBoundsException

Issue - State: open - Opened by hqjenny almost 9 years ago - 2 comments

#691 - Added blocks for input, output, and input-output timing closure

Pull Request - State: open - Opened by hutch31 almost 9 years ago - 8 comments

#690 - Fixed AsyncFifo so reset not tied to 0

Pull Request - State: open - Opened by da-steve101 almost 9 years ago - 4 comments

#689 - Chisel.TestApplicationException: test application exit - exit code 139

Issue - State: open - Opened by ascenium almost 9 years ago - 4 comments

#688 - Fix memory access masking bug for nonPow2 memories

Pull Request - State: closed - Opened by ccelio almost 9 years ago - 3 comments

#687 - do not extract a single bit wire

Pull Request - State: closed - Opened by donggyukim almost 9 years ago

#686 - Warning message needed?

Issue - State: open - Opened by da-steve101 almost 9 years ago

#685 - The <> operator and overriding

Issue - State: closed - Opened by da-steve101 almost 9 years ago - 1 comment

#684 - Tester observer

Pull Request - State: closed - Opened by ucbjrl almost 9 years ago

#683 - Added a pokePart method to Tester

Pull Request - State: closed - Opened by JackDavidson almost 9 years ago - 4 comments

#682 - Tester observer

Pull Request - State: closed - Opened by donggyukim almost 9 years ago

#681 - Changed index literals to base 10

Pull Request - State: closed - Opened by JackDavidson almost 9 years ago - 2 comments

#680 - Move tutorial doc to chisel-tutorial.

Pull Request - State: closed - Opened by ucbjrl almost 9 years ago

#679 - Corrected bit width of indexes into wires in verilog

Pull Request - State: closed - Opened by JackDavidson almost 9 years ago - 8 comments

#678 - C simulation left running if exception in tester

Issue - State: closed - Opened by da-steve101 almost 9 years ago - 1 comment

#677 - Verilog Address Widths Incorrect

Issue - State: closed - Opened by JackDavidson almost 9 years ago - 8 comments

#676 - Another printf output fix

Pull Request - State: closed - Opened by ucbjrl almost 9 years ago

#675 - Make Printf Cycle Accurate

Issue - State: closed - Opened by da-steve101 almost 9 years ago - 2 comments

#674 - Cocotb directives in Verilog backend

Issue - State: open - Opened by Martoni almost 9 years ago - 2 comments

#673 - A question on design

Issue - State: closed - Opened by da-steve101 almost 9 years ago - 8 comments

#672 - Width should grow when adding

Issue - State: closed - Opened by da-steve101 almost 9 years ago - 13 comments
Labels: Feature Request

#671 - Fix broken printf, newTestOutputString called multiple times

Pull Request - State: closed - Opened by da-steve101 almost 9 years ago - 11 comments

#669 - Changed Vec cloneType

Pull Request - State: open - Opened by shunshou almost 9 years ago - 11 comments

#668 - Invalid Reg width generation leads to bad bounds in generated Verilog

Issue - State: open - Opened by ccelio almost 9 years ago - 8 comments

#666 - Don't initialize the channels until we know how big they need to be - #665

Pull Request - State: closed - Opened by ucbjrl almost 9 years ago - 1 comment

#665 - Segmentation fault crashing tester

Issue - State: open - Opened by da-steve101 almost 9 years ago - 3 comments

#654 - Register size inference

Issue - State: open - Opened by schoeberl almost 9 years ago - 12 comments

#649 - Extract621 - use backend support for Extract() #621

Pull Request - State: closed - Opened by ucbjrl almost 9 years ago

#647 - Chisel3 unit tester

Pull Request - State: closed - Opened by ucbjrl about 9 years ago

#634 - Java Thread Deaths with Tester

Issue - State: closed - Opened by cyarp about 9 years ago - 2 comments

#617 - emit C++ local declarations at head of method

Pull Request - State: closed - Opened by ucbjrl about 9 years ago - 5 comments

#584 - Added an equal bits method

Pull Request - State: closed - Opened by da-steve101 about 9 years ago - 3 comments

#549 - Support for asynchronous resets in Verilog backend

Issue - State: closed - Opened by jwright6323 over 9 years ago - 2 comments
Labels: Feature Request, Verilog backend

#508 - Clock name as argument is not set in verilog backend

Issue - State: closed - Opened by Martoni over 9 years ago - 8 comments

#492 - Added a setModuleName method to Module

Pull Request - State: closed - Opened by da-steve101 over 9 years ago

#489 - Floating-point related inaccuracy in log2 functions

Issue - State: closed - Opened by zhemao over 9 years ago - 4 comments

#486 - Added some error checking for redeclarations

Pull Request - State: closed - Opened by da-steve101 over 9 years ago

#485 - Added a setName method to Module to resolve #478

Pull Request - State: closed - Opened by da-steve101 over 9 years ago - 1 comment

#356 - "expect" results a false PASS on wide data

Issue - State: closed - Opened by kammoh about 10 years ago

#314 - Feature : verilog's signals parameter ex : (* KEEP = "TRUE" *)

Issue - State: open - Opened by Dolu1990 over 10 years ago - 1 comment

#308 - Should be possible to configure a module without using --configInstance [string]

Issue - State: open - Opened by sdtwigg over 10 years ago - 1 comment
Labels: Feature Request

#180 - NullPointerException in Tester Doesn't Kill C++ Process

Issue - State: closed - Opened by ffard-lbl almost 11 years ago - 3 comments