Ecosyste.ms: Issues

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GitHub / ucb-bar/chisel-awl issues and pull requests

#20 - register select data before do ROM lookup to help timing

Pull Request - State: closed - Opened by linuxbest about 4 years ago

#19 - Rename to "chis-awl"?

Issue - State: open - Opened by jackkoenig almost 5 years ago

#18 - Make HasTLController generic to MultiIOModules

Pull Request - State: open - Opened by harrisonliew about 5 years ago

#17 - Chipyard compatibility

Pull Request - State: closed - Opened by harrisonliew about 5 years ago

#16 - Add near and far-end loopback debug modules

Issue - State: open - Opened by jwright6323 over 5 years ago

#15 - output lane divided clocks

Pull Request - State: closed - Opened by abejgonzalez over 5 years ago
Labels: enhancement

#14 - Pattern memory MMIO address mangling

Issue - State: open - Opened by jwright6323 over 5 years ago
Labels: bug

#13 - HBWIF Simulation Deserialization Bug

Issue - State: open - Opened by abejgonzalez over 5 years ago
Labels: bug

#12 - Add pattern/snapshot mems to the data interface

Issue - State: open - Opened by jwright6323 over 5 years ago

#12 - Add pattern/snapshot mems to the data interface

Issue - State: open - Opened by jwright6323 over 5 years ago

#11 - Add extra utilities | RC Update

Pull Request - State: closed - Opened by abejgonzalez over 5 years ago - 1 comment
Labels: enhancement

#10 - added a clock to differential class

Pull Request - State: closed - Opened by abejgonzalez over 5 years ago - 3 comments

#9 - Refactor for new name and rebar friendliness

Pull Request - State: open - Opened by jwright6323 almost 6 years ago

#8 - Make data factory parameter vals so cloneType can be inferred

Pull Request - State: closed - Opened by harrisonliew almost 6 years ago

#8 - Make data factory parameter vals so cloneType can be inferred

Pull Request - State: closed - Opened by harrisonliew almost 6 years ago

#7 - Refactor

Issue - State: open - Opened by jwright6323 about 6 years ago

#7 - Refactor

Issue - State: open - Opened by jwright6323 about 6 years ago

#6 - Negotiate bitwidths with far-side

Issue - State: open - Opened by jwright6323 over 6 years ago

#6 - Negotiate bitwidths with far-side

Issue - State: open - Opened by jwright6323 over 6 years ago

#5 - Create a Bert Unit Test

Issue - State: closed - Opened by jwright6323 almost 7 years ago

#4 - Can chisel do 1-indexed Vecs?

Issue - State: closed - Opened by jwright6323 almost 7 years ago - 4 comments

#4 - Can chisel do 1-indexed Vecs?

Issue - State: closed - Opened by jwright6323 almost 7 years ago - 4 comments

#3 - Resets

Issue - State: closed - Opened by jwright6323 almost 7 years ago

#3 - Resets

Issue - State: closed - Opened by jwright6323 almost 7 years ago

#2 - TileLink Backend Features

Issue - State: open - Opened by jwright6323 almost 7 years ago

#1 - Fixes for current versions of chisel and firrtl.

Pull Request - State: closed - Opened by jwright6323 almost 7 years ago - 1 comment

#1 - Fixes for current versions of chisel and firrtl.

Pull Request - State: closed - Opened by jwright6323 almost 7 years ago - 1 comment