Ecosyste.ms: Issues
An open API service for providing issue and pull request metadata for open source projects.
GitHub / tpoikela/uvm-python issues and pull requests
#54 - How to generate file dumpwave by code uvm-python?
Issue -
State: open - Opened by AnhHonag 3 months ago
#53 - It seems there are some problems in starting the sequence by using the way of UVMConfigDb.set(self, "xxx.xxx_vsqr.main_phase", "default_sequence", self.vseq ).
Issue -
State: open - Opened by 717-yq 3 months ago
- 3 comments
#52 - how should I use the force function in the UVM-Python verification environment, or is there a similar function to force in UVM-Python?
Issue -
State: closed - Opened by 717-yq 8 months ago
- 2 comments
#51 - Do you support uvm_component_param_utils? Any alternative approach? Any example?
Issue -
State: open - Opened by sbhutada 10 months ago
- 3 comments
#50 - examples/sv is failing ... any ideas?
Issue -
State: open - Opened by sbhutada 11 months ago
- 1 comment
#49 - Any example that shows integrating C++/SystemC predictor?
Issue -
State: closed - Opened by sbhutada 11 months ago
- 1 comment
#48 - Should we use PyVSC with UVM-Python to get constrained random and coverage working? Or, is there something similar already in the library?
Issue -
State: closed - Opened by sbhutada 11 months ago
- 1 comment
#47 - Is there a way to mix SystemVerilog UVM and UVM-Python environments?
Issue -
State: open - Opened by sbhutada 11 months ago
- 2 comments
#46 - Using uvm-python for with custom build infrastructure
Issue -
State: closed - Opened by sbhutada 11 months ago
- 4 comments
#45 - uvm_do doesn't work
Issue -
State: closed - Opened by M0stafaRady 12 months ago
- 2 comments
#44 - Test failing
Issue -
State: closed - Opened by psumesh over 1 year ago
- 1 comment
#43 - bit bash sequence crash on slave error fixed now
Pull Request -
State: closed - Opened by SikoVerilog over 1 year ago
- 1 comment
#42 - uvm_reg_hw_reset_sequence resolve status error on UVM_NOT_OK
Pull Request -
State: closed - Opened by SikoVerilog over 1 year ago
#41 - uvm hw reset sequence bug
Issue -
State: open - Opened by SikoVerilog over 1 year ago
- 2 comments
#40 - Cross TLM communication
Issue -
State: closed - Opened by psumesh over 1 year ago
- 2 comments
#39 - test uvm-python/test/examples/integrated/ubus/examples for "read modify write" can not be randomized with the uvm_do_with
Issue -
State: closed - Opened by ogheri over 3 years ago
- 3 comments
#38 - Small Markdown fixes in the Related projects section of README.md
Pull Request -
State: closed - Opened by rodrigomelo9 over 3 years ago
#37 - Latest version of cocotb Verilator will always issue error %Error-TIMESCALEMOD.
Issue -
State: open - Opened by jg-fossh over 3 years ago
- 4 comments
#36 - Correct way to clean up UVM objects
Issue -
State: open - Opened by sjalloq almost 4 years ago
- 2 comments
#35 - Fix for tpoikela/uvm-python#34
Pull Request -
State: closed - Opened by sjalloq almost 4 years ago
- 1 comment
#34 - Typo in uvm_reg_field.py
Issue -
State: closed - Opened by sjalloq almost 4 years ago
- 2 comments
#33 - Fix for Issue #32
Pull Request -
State: closed - Opened by sjalloq almost 4 years ago
- 4 comments
#32 - Bug in uvm_reg_map.py
Issue -
State: closed - Opened by sjalloq almost 4 years ago
- 3 comments
#31 - Adding __repr__() method to object_utils
Pull Request -
State: closed - Opened by sjalloq almost 4 years ago
#30 - Adding UVM_ELEMENT_KIND_NAMES
Pull Request -
State: closed - Opened by sjalloq almost 4 years ago
#29 - Fixing typo in uvm_reg_block.py
Pull Request -
State: closed - Opened by sjalloq almost 4 years ago
- 1 comment
#28 - What is the correct way to update the mirrored state of a register?
Issue -
State: closed - Opened by sjalloq almost 4 years ago
- 7 comments
#27 - Documentation rendering issue
Issue -
State: closed - Opened by sjalloq almost 4 years ago
- 7 comments
#26 - registers/vertical_reuse blk-level simulation fails with ghdl/VHDL DUT
Issue -
State: open - Opened by tpoikela almost 4 years ago
- 11 comments
#25 - Add more files to ignore from cocotb's version
Pull Request -
State: closed - Opened by cmarqu almost 4 years ago
#24 - Add some VHDL DUTs
Pull Request -
State: closed - Opened by cmarqu almost 4 years ago
- 9 comments
#23 - Change commercial -> proprietary
Pull Request -
State: closed - Opened by mgielda about 4 years ago
- 1 comment
#22 - UVM Python minimal test
Issue -
State: closed - Opened by tsengr0916 over 4 years ago
- 6 comments
#21 - uvm_info
Issue -
State: closed - Opened by zfling over 4 years ago
- 6 comments
#20 - Remove Makefile.inc inclusion which is deprecated in cocotb master
Pull Request -
State: closed - Opened by cmarqu over 4 years ago
#19 - Fix missing async; remove unconditional VCD dump
Pull Request -
State: closed - Opened by cmarqu over 4 years ago
#18 - Fixes required for commercial simulators
Pull Request -
State: closed - Opened by cmarqu over 4 years ago
#17 - Add more simulator output files to .gitignore
Pull Request -
State: closed - Opened by cmarqu over 4 years ago
- 1 comment
#16 - Fix package building
Pull Request -
State: closed - Opened by cmarqu over 4 years ago
#15 - type error
Issue -
State: closed - Opened by zfling over 4 years ago
- 11 comments
#14 - Failed to import module new_test: No module named 'uvm'
Issue -
State: closed - Opened by zfling over 4 years ago
- 8 comments
#13 - Rename UVMTlm classes to UVMTLM
Pull Request -
State: closed - Opened by mballance almost 5 years ago
#12 - Allow uvm_object_utils and uvm_component_utils to be used a decorators
Pull Request -
State: closed - Opened by mballance almost 5 years ago
- 1 comment
#11 - Initial TLM2 Implementation
Pull Request -
State: closed - Opened by mballance almost 5 years ago
- 7 comments
#10 - Add a 'wait()' utility method
Pull Request -
State: closed - Opened by mballance almost 5 years ago
- 1 comment
#9 - modify implementation of 'wait' in m_wait_for_arbitration_completed
Pull Request -
State: closed - Opened by mballance almost 5 years ago
#8 - Add more metadata; run black formatter
Pull Request -
State: closed - Opened by cmarqu almost 5 years ago
#7 - Use default role 'any' to ease conversion from Natural Docs
Pull Request -
State: closed - Opened by cmarqu almost 5 years ago
#6 - Use simulator name and version, as reported to cocotb via vpi
Pull Request -
State: closed - Opened by mballance almost 5 years ago
#5 - Copy structure from UVM-SV API docs
Pull Request -
State: closed - Opened by cmarqu almost 5 years ago
- 2 comments
#4 - Move 'uvm' package directory into a containing 'src' directory
Pull Request -
State: closed - Opened by mballance almost 5 years ago
#3 - Add setup for documentation with Sphinx
Pull Request -
State: closed - Opened by cmarqu almost 5 years ago
- 2 comments
#2 - Fix small things, part 2
Pull Request -
State: closed - Opened by cmarqu almost 5 years ago
#1 - Fix small things
Pull Request -
State: closed - Opened by cmarqu almost 5 years ago
- 1 comment