Ecosyste.ms: Issues
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GitHub / textmate/verilog.tmbundle issues and pull requests
#2 - Verilog: multiple port/wire/reg declarations per line results in misanalysis
Issue -
State: open - Opened by birdybro about 2 years ago
#1 - Add 'generate/endgenerate' pair and 'genvar' to keyword list
Pull Request -
State: closed - Opened by mshr-h about 9 years ago
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