Ecosyste.ms: Issues
An open API service for providing issue and pull request metadata for open source projects.
GitHub / steveicarus/iverilog issues and pull requests
#53 - {256'b0}[ADDR-1:0]; Syntax error
Issue -
State: closed - Opened by abhisheietk almost 10 years ago
- 5 comments
#52 - Unbounded vectors in VHDL functions.
Pull Request -
State: closed - Opened by orsonmmz almost 10 years ago
#51 - Vhdl range func
Pull Request -
State: closed - Opened by orsonmmz almost 10 years ago
- 2 comments
#50 - Unpacked arrays extension
Pull Request -
State: closed - Opened by orsonmmz almost 10 years ago
#49 - Support for dynamic arrays in the VPI
Pull Request -
State: closed - Opened by orsonmmz almost 10 years ago
#48 - SystemVerilog 'b0 construct for flexible padding?
Issue -
State: closed - Opened by mbsullivan about 10 years ago
- 1 comment
#47 - Expression concatenation in VHDL
Pull Request -
State: closed - Opened by orsonmmz about 10 years ago
#46 - VHDL attributes: 'range, 'reverse_range, 'left & 'right
Pull Request -
State: closed - Opened by orsonmmz about 10 years ago
#45 - Subprograms
Pull Request -
State: closed - Opened by orsonmmz about 10 years ago
#44 - gperf generated code fails debug build with CFLAGS/CXXFLAGS="-O0 -g"
Issue -
State: closed - Opened by ghost about 10 years ago
- 5 comments
#43 - Elaboration & emit functions for aggregate expressions used as record initializers.
Pull Request -
State: closed - Opened by orsonmmz about 10 years ago
- 6 comments
#42 - Enable constant initializers that require elaboration in packages.
Pull Request -
State: closed - Opened by orsonmmz about 10 years ago
#41 - Strange "localparam integer" behavior
Issue -
State: closed - Opened by cliffordwolf about 10 years ago
- 7 comments
#40 - Version number is incorrect when build from source.
Issue -
State: closed - Opened by dkozel about 10 years ago
- 6 comments
#39 - Fixed enum typedefs.
Pull Request -
State: closed - Opened by orsonmmz about 10 years ago
#38 - Support for VHDL unbounded arrays.
Pull Request -
State: closed - Opened by orsonmmz over 10 years ago
#37 - Another "size of unsized constant" bug
Issue -
State: closed - Opened by cliffordwolf over 10 years ago
- 2 comments
#36 - synthesis translate_{off,on} inside behavioral code
Issue -
State: closed - Opened by cliffordwolf over 10 years ago
- 4 comments
#35 - Removed ExpReal::evaluate().
Pull Request -
State: closed - Opened by orsonmmz over 10 years ago
#34 - Assertion `lval_->more == 0' failed
Issue -
State: closed - Opened by ghost over 10 years ago
- 5 comments
#33 - Problem with multi-dimensional arrays
Issue -
State: closed - Opened by cliffordwolf over 10 years ago
- 5 comments
#32 - Real type support for vhdlpp.
Pull Request -
State: closed - Opened by orsonmmz over 10 years ago
#31 - Bug, no bug, or just undefined, that is the question (real vs. signed and unsigned int)
Issue -
State: closed - Opened by cliffordwolf over 10 years ago
- 4 comments
#30 - failed assertion rval.len() == wid in eval_tree.cc:1029:
Issue -
State: closed - Opened by cliffordwolf over 10 years ago
- 2 comments
#29 - module Input ports are unconnected...
Issue -
State: closed - Opened by ghost over 10 years ago
- 4 comments
#28 - Insufficient string escaping when writing vvp script
Issue -
State: closed - Opened by cliffordwolf over 10 years ago
- 1 comment
#27 - Default minval for $urandom_range() not supported
Issue -
State: closed - Opened by bobnewgard over 10 years ago
- 5 comments
#26 - Another assert for invalid input
Issue -
State: closed - Opened by cliffordwolf over 10 years ago
- 1 comment
#25 - Assert (instead of error message) for function outside module
Issue -
State: closed - Opened by cliffordwolf over 10 years ago
- 8 comments
#24 - iverilog gives no warning against dangling wires within a module
Issue -
State: closed - Opened by dword1511 over 10 years ago
- 9 comments
#23 - iverilog allows use before declaration
Issue -
State: closed - Opened by dword1511 over 10 years ago
- 1 comment
#22 - Another strange icarus expression eval bug (large shifts)
Issue -
State: closed - Opened by cliffordwolf over 10 years ago
- 4 comments
#21 - package imports in module headers
Pull Request -
State: closed - Opened by toddstrader over 10 years ago
#20 - Icarus confused about signed/unsigned in strange ?: example
Issue -
State: closed - Opened by cliffordwolf over 10 years ago
- 1 comment
#19 - Icarus only using the lowest 32 bits of right shift operand
Issue -
State: closed - Opened by cliffordwolf over 10 years ago
- 10 comments
#18 - Icarus does undef propagation of const multiplies incorrectly
Issue -
State: closed - Opened by cliffordwolf over 10 years ago
- 2 comments
#17 - Completion of error handling
Issue -
State: closed - Opened by elfring over 10 years ago
- 4 comments
#16 - reserved identifier violation
Issue -
State: closed - Opened by elfring over 10 years ago
- 9 comments
#15 - Icarus does undef propagation of const adds incorrectly
Issue -
State: closed - Opened by cliffordwolf almost 11 years ago
- 2 comments
#14 - Icarus Verilog bug in processing "1'b1 >= |1'bx"
Issue -
State: closed - Opened by cliffordwolf almost 11 years ago
- 1 comment
#13 - Icarus Verilog creates huge in-memory arrays for shifts with large rhs
Issue -
State: closed - Opened by cliffordwolf almost 11 years ago
- 7 comments
#12 - internal error: lval-rval width mismatch
Issue -
State: closed - Opened by cliffordwolf almost 11 years ago
- 1 comment
#11 - Syntax error on operator attributes.
Issue -
State: closed - Opened by cliffordwolf almost 11 years ago
- 1 comment
#10 - Fixed homepage link
Pull Request -
State: closed - Opened by kiteflyingmonkey almost 11 years ago
#9 - Efficiency of verinum and vpp_net pow() functions
Issue -
State: closed - Opened by cliffordwolf almost 11 years ago
- 8 comments
#8 - Signedness handling in binary bitwise operations of constants
Issue -
State: closed - Opened by cliffordwolf almost 11 years ago
- 2 comments
#7 - Undef propagation in power operator
Issue -
State: closed - Opened by cliffordwolf almost 11 years ago
- 2 comments
#6 - vvp asserts on reduce of one-bit .arith/sub
Issue -
State: closed - Opened by cliffordwolf almost 11 years ago
- 2 comments
#5 - Added missing support for binary ^~ in eval_tree.cc
Pull Request -
State: closed - Opened by cliffordwolf almost 11 years ago
- 1 comment
#4 - Simple class usage
Issue -
State: closed - Opened by getvictor about 11 years ago
- 6 comments
#3 - How to flush output to stdout with vvp?
Issue -
State: closed - Opened by getvictor over 11 years ago
- 10 comments
#2 - Concatenation seemingly not using full width
Issue -
State: closed - Opened by ysangkok almost 12 years ago
#1 - out of date FSF address
Issue -
State: closed - Opened by arunpersaud about 12 years ago
- 3 comments