Ecosyste.ms: Issues
An open API service for providing issue and pull request metadata for open source projects.
GitHub / stanford-ppl/spatial-lang issues and pull requests
#267 - Build dependencies not listed
Issue -
State: closed - Opened by rachitnigam almost 6 years ago
- 3 comments
#266 - generating hdl/design_1.v error while making zynq
Issue -
State: closed - Opened by ShaopengChen about 6 years ago
- 2 comments
#265 - LUT initial value inline might cause java byte code limit in pirgen
Issue -
State: closed - Opened by yaqiz01 over 6 years ago
- 1 comment
Labels: bug
#264 - Aligned load becomes unaligned load because of type conversion
Issue -
State: open - Opened by yaqiz01 over 6 years ago
Labels: bug
#263 - Reduction with 0 loop iterations is not well defined
Issue -
State: open - Opened by dkoeplin over 6 years ago
- 5 comments
Labels: bug, enhancement
#262 - Add ZCU102 DeviceTarget in Chisel generator's Util.scala template.
Pull Request -
State: open - Opened by timran1 over 6 years ago
#261 - Moving to [SGN, WIDTH, OFFSET] Representation for FixPt
Issue -
State: open - Opened by mattfel1 over 6 years ago
- 1 comment
#260 - API for unbiased and saturating casting
Issue -
State: open - Opened by mattfel1 over 6 years ago
- 1 comment
#259 - Accel Inside Loop
Issue -
State: closed - Opened by mattfel1 over 6 years ago
- 3 comments
#258 - Cat API
Issue -
State: open - Opened by mattfel1 almost 7 years ago
- 1 comment
#257 - Proper Control Flow for FIR filter
Issue -
State: open - Opened by mattfel1 almost 7 years ago
#256 - move streamId to tag and expand Zynq tag width to 32 bits
Pull Request -
State: closed - Opened by mattvilim almost 7 years ago
#255 - Warn or Error if Trying to Read to ArgOut in Accel
Issue -
State: open - Opened by mattfel1 almost 7 years ago
- 3 comments
#254 - Automatically Add "--help" to Generated Code
Issue -
State: closed - Opened by mattfel1 almost 7 years ago
- 1 comment
Labels: enhancement
#253 - Implement Spatial ILA for On-Board Waveform Debugging
Issue -
State: open - Opened by mattfel1 almost 7 years ago
- 3 comments
Labels: enhancement
#252 - Fix this chisel warning
Issue -
State: closed - Opened by mattfel1 almost 7 years ago
- 2 comments
#251 - Time-critical Switch Conditions Busted with Retiming
Issue -
State: closed - Opened by mattfel1 almost 7 years ago
- 1 comment
#250 - add scatter/gather debug registers
Pull Request -
State: closed - Opened by mattvilim almost 7 years ago
- 1 comment
#249 - AWS Fringe: Support 4 DRAM Channels
Issue -
State: open - Opened by shadjis almost 7 years ago
#248 - Update Makefile
Pull Request -
State: closed - Opened by dkoeplin almost 7 years ago
- 1 comment
#247 - Special-case dense load/store channels
Issue -
State: closed - Opened by shadjis almost 7 years ago
- 1 comment
#246 - Throw warning for parallelized, unaligned loads into LineBuffer or rethink template
Issue -
State: open - Opened by mattfel1 almost 7 years ago
#245 - Added scatter/gather support in Fringe
Pull Request -
State: closed - Opened by mattvilim almost 7 years ago
- 5 comments
#244 - Scheduling of Switch Inside Parallel
Issue -
State: closed - Opened by mattfel1 almost 7 years ago
- 3 comments
#243 - VCS Issue with 1D DRAMs allocated after 4D DRAM
Issue -
State: closed - Opened by mattfel1 almost 7 years ago
- 1 comment
#242 - Partial Mem Reduce
Issue -
State: closed - Opened by mattfel1 almost 7 years ago
- 2 comments
#241 - Fringe Command Fifo Filling Glitch
Issue -
State: closed - Opened by mattfel1 about 7 years ago
- 1 comment
#240 - PageRank Compiler Error
Issue -
State: closed - Opened by yaqiz01 about 7 years ago
Labels: bug
#239 - Latched Values of RegFile over AXI
Issue -
State: open - Opened by mattfel1 about 7 years ago
#238 - Spatial compiler crashes when cgra+ is enabled
Issue -
State: closed - Opened by yaqiz01 about 7 years ago
Labels: bug
#237 - Mux between memories
Issue -
State: open - Opened by mattfel1 about 7 years ago
#236 - Add Target-dependent file input for latency model
Issue -
State: closed - Opened by dkoeplin about 7 years ago
- 1 comment
#235 - Bump up Div/Mul Latency for Ops with Fractions
Issue -
State: closed - Opened by mattfel1 about 7 years ago
- 1 comment
#234 - Fringe Glitch
Issue -
State: closed - Opened by mattfel1 about 7 years ago
- 1 comment
#233 - Improve counter area (e.g. DSPs)
Issue -
State: closed - Opened by shadjis about 7 years ago
- 1 comment
#232 - Use MACC IP
Issue -
State: open - Opened by shadjis about 7 years ago
- 3 comments
#231 - Improve ultra ram width utilization
Issue -
State: open - Opened by shadjis about 7 years ago
#230 - Use URAMs on F1
Issue -
State: open - Opened by shadjis about 7 years ago
- 6 comments
#229 - Metadata issues when pirgen is enabled
Issue -
State: closed - Opened by yaqiz01 about 7 years ago
Labels: bug
#228 - Naughty Usage of LineBuffer, Should We Throw Warning?
Issue -
State: open - Opened by mattfel1 about 7 years ago
#227 - Why Did Suppressing a LineBuffer .rotate in Scala Fix Convolutions?
Issue -
State: closed - Opened by mattfel1 about 7 years ago
- 2 comments
#226 - Banking and Dispatch Strangeness
Issue -
State: open - Opened by mattfel1 about 7 years ago
#225 - Dimension as Function of DSE Parameters
Issue -
State: closed - Opened by mattfel1 about 7 years ago
- 2 comments
Labels: enhancement
#224 - Incorrectly Code Motioned
Issue -
State: closed - Opened by mattfel1 about 7 years ago
- 1 comment
#223 - General Banking Support
Issue -
State: closed - Opened by yaqiz01 about 7 years ago
Labels: enhancement
#222 - ScopeCheck sees DRAM dimension access as illegal input
Issue -
State: closed - Opened by mattfel1 about 7 years ago
- 1 comment
#221 - Use real latencies for compacting fifos
Issue -
State: open - Opened by mattfel1 about 7 years ago
#220 - AccessDispatch has more than one dispatch
Issue -
State: open - Opened by mattfel1 about 7 years ago
- 2 comments
#219 - Updates for Plasticine
Issue -
State: open - Opened by dkoeplin about 7 years ago
- 6 comments
Labels: enhancement
#218 - Systolic Array support
Issue -
State: open - Opened by mattfel1 about 7 years ago
Labels: enhancement
#217 - Cheaper SRAM
Issue -
State: open - Opened by mattfel1 about 7 years ago
#216 - Compacting Fifo
Issue -
State: closed - Opened by mattfel1 about 7 years ago
- 2 comments
#215 - Throw Exception About Unused Args/DRAMs
Issue -
State: closed - Opened by mattfel1 about 7 years ago
- 2 comments
#214 - Stream vcs
Pull Request -
State: open - Opened by swamy-t about 7 years ago
- 1 comment
#213 - Relaxed En/Done Protocol Breaks FSM
Issue -
State: closed - Opened by mattfel1 about 7 years ago
#212 - Load/Store on part of struct
Issue -
State: open - Opened by mattfel1 about 7 years ago
- 1 comment
Labels: enhancement, discuss
#211 - Nonexistent Bound Syms in Certain Cases
Issue -
State: closed - Opened by mattfel1 about 7 years ago
- 1 comment
#210 - One-Hot Mux for DRAM Addressing is Not Buffered Correctly
Issue -
State: closed - Opened by mattfel1 over 7 years ago
- 3 comments
#209 - Certain Unaligned Loads/Stores to Fifos/Stacks Hang
Issue -
State: closed - Opened by mattfel1 over 7 years ago
- 1 comment
#208 - Retime in Reduce Loop
Issue -
State: closed - Opened by mattfel1 over 7 years ago
#207 - Strange retime bug
Issue -
State: closed - Opened by mattfel1 over 7 years ago
- 1 comment
#206 - Convert Mods of Power 2 to Slice-Casts
Issue -
State: closed - Opened by mattfel1 over 7 years ago
- 3 comments
Labels: enhancement
#205 - Fringe Issues Multiple Commands for same address
Issue -
State: closed - Opened by mattfel1 over 7 years ago
- 1 comment
#204 - II for Innerpipe FSM Wrong
Issue -
State: open - Opened by mattfel1 over 7 years ago
- 2 comments
Labels: bug, awaiting test
#203 - Access Dispatch Strangeness
Issue -
State: closed - Opened by mattfel1 over 7 years ago
- 2 comments
#202 - iiOf seems wrong for fifo operations
Issue -
State: closed - Opened by mattfel1 over 7 years ago
- 3 comments
#201 - Kmeans_plasticine IR RegWrite Bug
Issue -
State: closed - Opened by yaqiz01 over 7 years ago
- 2 comments
Labels: bug
#200 - Banking analysis
Issue -
State: closed - Opened by yaqiz01 over 7 years ago
- 2 comments
Labels: enhancement
#199 - Look into NumIter Retiming
Issue -
State: closed - Opened by mattfel1 over 7 years ago
- 1 comment
#198 - Chisel file splitting bug
Issue -
State: closed - Opened by dkoeplin over 7 years ago
- 1 comment
Labels: bug
#197 - linebuf banking
Issue -
State: closed - Opened by shadjis over 7 years ago
- 1 comment
#196 - interpreter update
Pull Request -
State: closed - Opened by rubenfiszel over 7 years ago
#195 - Unaligned Store Messed Up (Why did it even work before?)
Issue -
State: closed - Opened by mattfel1 over 7 years ago
- 1 comment
#194 - Implicitly change RegRead and RegWrite outside Accel to getArg and setArg (and vice versa?)
Issue -
State: closed - Opened by mattfel1 over 7 years ago
- 1 comment
Labels: enhancement
#193 - Splitting of UnitPipe in pirgen
Issue -
State: closed - Opened by yaqiz01 over 7 years ago
Labels: enhancement
#192 - Initial value load for accumulation
Issue -
State: closed - Opened by yaqiz01 over 7 years ago
Labels: bug
#191 - Add untested area extraction code
Pull Request -
State: closed - Opened by rmu2 over 7 years ago
#190 - HostIO Read is "Exact(_)" If Set Inside the Accel
Issue -
State: closed - Opened by mattfel1 over 7 years ago
- 1 comment
#187 - Incorrect DiagonalMemory in Gibbs_Ising2D
Issue -
State: closed - Opened by mattfel1 over 7 years ago
- 1 comment
#183 - Initiation interval calculation problems
Issue -
State: open - Opened by dkoeplin over 7 years ago
- 2 comments
Labels: bug, enhancement
#178 - MatMult_inner banking
Issue -
State: closed - Opened by yaqiz01 over 7 years ago
- 1 comment
Labels: bug
#176 - Initiation Interval Mistake For Loop Carry Dependencies
Issue -
State: closed - Opened by mattfel1 over 7 years ago
- 1 comment
#175 - Interpreter
Pull Request -
State: closed - Opened by rubenfiszel over 7 years ago
#173 - Missing operations on FixPt
Issue -
State: open - Opened by rubenfiszel over 7 years ago
- 1 comment
Labels: enhancement
#171 - Use fewer SRAMs in Fringe
Issue -
State: closed - Opened by shadjis over 7 years ago
- 1 comment
Labels: enhancement
#167 - Improve FixPt and FltPt const type
Issue -
State: open - Opened by rubenfiszel over 7 years ago
- 2 comments
Labels: enhancement
#165 - Remove Potentially Unnecessary Pipe from alignedStore
Issue -
State: open - Opened by mattfel1 over 7 years ago
- 2 comments
Labels: awaiting test
#164 - init interval optimization
Issue -
State: closed - Opened by mattfel1 over 7 years ago
- 1 comment
#159 - Add support for generalized affine access patterns (more than 1 index)
Issue -
State: closed - Opened by mattfel1 over 7 years ago
- 2 comments
Labels: enhancement
#151 - Reduction not inferred in NW?
Issue -
State: closed - Opened by mattfel1 over 7 years ago
- 2 comments
#139 - Support compacting fifo
Issue -
State: closed - Opened by mattfel1 over 7 years ago
- 2 comments
#103 - Add a way of pausing the FPGA
Issue -
State: closed - Opened by kelayamatoz over 7 years ago
- 1 comment
Labels: enhancement
#99 - Add break api
Issue -
State: closed - Opened by mattfel1 over 7 years ago
- 3 comments
#86 - Add stride to linebuf and shift reg
Issue -
State: open - Opened by shadjis over 7 years ago
- 3 comments
Labels: enhancement
#71 - scalameta upcoming features
Issue -
State: open - Opened by rubenfiszel over 7 years ago
- 1 comment
#67 - Scala LineBuffer Template Rotation Signals
Issue -
State: closed - Opened by mattfel1 over 7 years ago
- 2 comments
Labels: bug
#60 - Repository Cruft
Issue -
State: open - Opened by dkoeplin over 7 years ago
Labels: cleanup
#55 - An OptiML frontend by integrating a Vector and Matrix API
Issue -
State: closed - Opened by rubenfiszel over 7 years ago
- 2 comments
Labels: enhancement
#27 - Freeze Chisel version to avoid surprises, perform explicit periodic upgrades
Issue -
State: closed - Opened by raghup17 over 7 years ago
- 1 comment
Labels: enhancement
#10 - schedule doesn't preserve reg read/write order?
Issue -
State: closed - Opened by yaqiz01 over 7 years ago
Labels: bug