spinalhdl/vexriscv issues and pull requests

#98 - WFI: System can't be reset via DebugPlugin

Issue - State: open - Opened by xobs about 5 years ago - 16 comments

#97 - Spec-compliant debug interface

Issue - State: open - Opened by MarekPikula about 5 years ago - 11 comments

#96 - Vectored interrupt support

Issue - State: open - Opened by MarekPikula about 5 years ago - 9 comments

#95 - Update index links in README

Pull Request - State: closed - Opened by MarekPikula about 5 years ago - 1 comment

#94 - Multiplication Plugin using 16-bit DSPs

Pull Request - State: closed - Opened by rpls about 5 years ago - 3 comments

#93 - RV32IMC with IBusCachedPlugin

Issue - State: open - Opened by MarekPikula about 5 years ago - 11 comments

#92 - Have you seen pqriscv-vexriscv?

Issue - State: open - Opened by mithro about 5 years ago - 1 comment

#91 - Tightly coupled memory

Issue - State: open - Opened by 9ary about 5 years ago - 6 comments

#90 - Issue connecting debug to simulated CPU

Issue - State: closed - Opened by sebastien-riou about 5 years ago - 3 comments

#89 - DPC and DCSR csrs for enabling Semihosting

Issue - State: closed - Opened by shufps about 5 years ago - 4 comments

#88 - Illegal instruction div, rem

Issue - State: closed - Opened by shufps about 5 years ago - 4 comments

#87 - Does mdd and mwd commands work with openocd_riscv?

Issue - State: closed - Opened by shufps about 5 years ago - 3 comments

#86 - Short pipeline fixes

Pull Request - State: closed - Opened by xobs about 5 years ago - 4 comments

#85 - Support multicore configurations

Issue - State: closed - Opened by mithro about 5 years ago - 8 comments

#84 - vexriscv.MuraxSim error in Windows 10 using the latest github clone

Issue - State: open - Opened by flylandcs about 5 years ago - 5 comments

#83 - RiscV A "AMO" with DBusSimplePlugin

Issue - State: open - Opened by BlamKiwi over 5 years ago - 3 comments

#82 - illegal instruction with Zephyr

Issue - State: open - Opened by FrankBuss over 5 years ago - 2 comments

#81 - Add support for fast register saving

Issue - State: open - Opened by mithro over 5 years ago - 3 comments

#80 - Fix handling LiteX uart and timer.

Pull Request - State: closed - Opened by mateusz-holenko over 5 years ago - 1 comment

#79 - Litex target

Pull Request - State: closed - Opened by mateusz-holenko over 5 years ago - 3 comments

#78 - Unused registers

Issue - State: open - Opened by dnltz over 5 years ago - 1 comment

#77 - Benchmark VexRISCV using embench

Issue - State: open - Opened by mithro over 5 years ago - 11 comments

#76 - Support for native BRAM instruction fetch bus

Issue - State: closed - Opened by smunaut over 5 years ago - 2 comments

#75 - Merge dev (SpinalHDL 1.3.4)

Pull Request - State: closed - Opened by Dolu1990 over 5 years ago

#74 - Add memory 2 stage

Pull Request - State: open - Opened by tomverbeure over 5 years ago - 1 comment

#73 - Issues with built-in DDR memory controller Briey SoC

Issue - State: closed - Opened by FlyingxDutch over 5 years ago - 5 comments

#72 - JTAG input clock has not buffer

Issue - State: closed - Opened by FlyingxDutch over 5 years ago - 3 comments

#71 - Mmu 2 stage

Pull Request - State: closed - Opened by xobs over 5 years ago - 1 comment

#70 - No trap generated for `divu` on core without divide

Issue - State: closed - Opened by xobs over 5 years ago - 13 comments

#69 - GenMicro with warnings

Pull Request - State: closed - Opened by tomverbeure over 5 years ago - 8 comments

#68 - Add a pipeline description to gcc

Issue - State: open - Opened by futaris over 5 years ago - 6 comments

#67 - Some minor updated to the manual

Pull Request - State: closed - Opened by tomverbeure over 5 years ago - 1 comment

#66 - Add getPipelinedMemoryBusConfig()

Pull Request - State: closed - Opened by tomverbeure over 5 years ago - 1 comment

#65 - Murax debug on FPGA

Issue - State: closed - Opened by sebastien-riou over 5 years ago - 5 comments

#64 - MulSimplePlugin

Pull Request - State: closed - Opened by tomverbeure over 5 years ago - 1 comment

#63 - Provide MMU / MemoryTranslatorPlugin example

Issue - State: open - Opened by xobs over 5 years ago - 5 comments

#62 - Redesign data cache to reduce area usage

Issue - State: closed - Opened by Dolu1990 over 5 years ago - 1 comment

#61 - Mul/Div don't work if withWriteBackStage or withMemoryStage is false

Issue - State: open - Opened by xobs over 5 years ago - 1 comment

#60 - Linux on VexRiscv

Issue - State: closed - Opened by ghost over 5 years ago - 345 comments

#59 - Incorrect path to examples

Issue - State: closed - Opened by secworks over 5 years ago - 4 comments

#58 - Fix image in README.

Pull Request - State: closed - Opened by mithro over 5 years ago - 1 comment

#57 - Two lint issues with the vexriscv.demo.GenFull configuration

Issue - State: closed - Opened by secworks over 5 years ago - 2 comments

#56 - Correct spelling?

Issue - State: open - Opened by secworks almost 6 years ago - 1 comment

#55 - Source for muraxDemo.hex

Issue - State: closed - Opened by lawrie almost 6 years ago - 2 comments

#54 - The smallest verilog simulation does not commit SW before RET. Anything wrong?

Issue - State: closed - Opened by wye1102 almost 6 years ago - 5 comments

#53 - Add APB3 to AXI Stream peripheral to Murax (with FIFO)

Pull Request - State: open - Opened by eine almost 6 years ago - 2 comments

#52 - [WIP] Docker images

Pull Request - State: closed - Opened by eine almost 6 years ago - 1 comment

#51 - Can't access the code memory when a breakpoint is set on it

Issue - State: closed - Opened by LukasJaegerSIT almost 6 years ago - 3 comments

#50 - [WIP] Sphinx-RTD

Pull Request - State: open - Opened by wifasoi almost 6 years ago - 1 comment

#49 - Avalon: Debug Clock Domain for JTAG

Pull Request - State: closed - Opened by cutephoton almost 6 years ago - 2 comments

#48 - JTAG/Reset Lock Up (Avalon)

Issue - State: closed - Opened by cutephoton almost 6 years ago - 16 comments

#47 - Create wiki

Issue - State: open - Opened by cutephoton almost 6 years ago - 11 comments

#46 - SEGV in regression test: Too many open files

Issue - State: closed - Opened by darkstar007 almost 6 years ago - 22 comments

#45 - Congratulations for winning 1st place of SoftCPU contest!

Issue - State: open - Opened by drom almost 6 years ago - 1 comment

#44 - CPU Generation Documentation in README

Issue - State: closed - Opened by ast96 almost 6 years ago - 1 comment

#43 - Can the Briey SoC run on a iCE40-HX8K-CT256?

Issue - State: closed - Opened by ndbroadbent almost 6 years ago - 4 comments

#42 - RV32E support

Issue - State: open - Opened by xobs about 6 years ago - 4 comments

#41 - Processor not writing to data memory

Issue - State: closed - Opened by yannickl96 about 6 years ago - 12 comments

#40 - Add support for using the DSP blocks on the iCE40UP5K?

Issue - State: closed - Opened by mithro about 6 years ago - 20 comments

#39 - Does it use physical address or virtual address?

Issue - State: closed - Opened by shibo-chen about 6 years ago - 1 comment

#38 - File name <> Module name inconsistent

Issue - State: open - Opened by tomverbeure over 6 years ago - 2 comments

#37 - VexRiscv configuration doesn't trap on misaligned branch

Issue - State: open - Opened by tomverbeure over 6 years ago - 1 comment

#36 - QSys interprets clock and reset as conduits

Issue - State: closed - Opened by kaofishy over 6 years ago - 5 comments

#35 - Problems when writing to memory

Issue - State: closed - Opened by yannickl96 over 6 years ago - 6 comments

#34 - More README fixes

Pull Request - State: closed - Opened by mithro over 6 years ago

#33 - Improve the Murax example for the iCE40-hx8k_breakout_board

Pull Request - State: closed - Opened by mithro over 6 years ago - 1 comment

#32 - What is the difference between iCE40HX8K-EVB and iCE40-hx8k_breakout_board

Issue - State: closed - Opened by mithro over 6 years ago - 4 comments

#31 - sbt "run-main vexriscv.demo.MuraxWithRamInit" does nothing?

Issue - State: closed - Opened by mithro over 6 years ago - 1 comment

#30 - Two minor fixes to README.md

Pull Request - State: closed - Opened by mithro over 6 years ago - 1 comment

#29 - README.md: add missing newline

Pull Request - State: closed - Opened by mcmasterg over 6 years ago - 2 comments

#28 - Can VexRISCV based SoC be made to fit on an iCE40 1k?

Issue - State: open - Opened by mithro over 6 years ago - 8 comments

#27 - README language

Pull Request - State: closed - Opened by tomverbeure over 6 years ago - 3 comments

#26 - Setup instructions: unable to build SpinalHDL

Issue - State: closed - Opened by xobs over 6 years ago - 6 comments

#25 - Setup instructions: Cannot install key

Issue - State: closed - Opened by xobs over 6 years ago - 6 comments

#24 - Fix some missing Barriel -> barriel fixes

Pull Request - State: closed - Opened by tomverbeure over 6 years ago - 1 comment

#23 - BarrielShifter -> BarrelShifter

Pull Request - State: closed - Opened by tomverbeure over 6 years ago - 1 comment

#22 - Briey DE0 Nano SoC, not enough I/O pin locations

Issue - State: open - Opened by Lestandin over 6 years ago - 3 comments

#21 - Typos...

Pull Request - State: closed - Opened by tomverbeure over 6 years ago - 1 comment

#20 - AXI Bridge

Issue - State: closed - Opened by yannickl96 over 6 years ago - 2 comments

#19 - Add iCE40 stats to "Area usage and maximal frequency" section?

Issue - State: closed - Opened by mithro over 6 years ago - 9 comments

#18 - Getting errors on running OpenOCD using Briey.scala cpu

Issue - State: closed - Opened by anuragktl over 6 years ago - 1 comment
Labels: Need more info

#17 - VexRiscV fails to meet timing as soon as you connect it to IBus/DBus memory

Issue - State: closed - Opened by ameetgohil over 6 years ago - 11 comments

#16 - Briey simulation regression

Issue - State: closed - Opened by m-chabot over 6 years ago - 6 comments

#15 - Construct Plugin-wrapped objects using Factories OR Parameterize

Issue - State: closed - Opened by drichmond almost 7 years ago - 11 comments

#14 - GenFullNoMmuNoCache throws exception with fence.i and fence

Issue - State: closed - Opened by esromneb almost 7 years ago - 3 comments

#13 - Unresolved dependency on eclipse plugin

Issue - State: closed - Opened by roman3017 almost 7 years ago - 2 comments

#12 - 48/64 bit instructions

Issue - State: open - Opened by drom almost 7 years ago - 2 comments
Labels: enhancement

#11 - Interactive debug of the simulated CPU

Issue - State: closed - Opened by shengbintai almost 7 years ago - 3 comments

#10 - Port to iCE40HX8K-EVB

Pull Request - State: closed - Opened by Wallbraker almost 7 years ago - 1 comment

#9 - Minor fixes to Murax.scala

Pull Request - State: closed - Opened by kaofishy about 7 years ago - 1 comment

#8 - Fixed an issue with bursted AXI Transactions on the ICache

Pull Request - State: closed - Opened by drichmond about 7 years ago - 16 comments

#7 - Xilinx Vivado inferring block ram on register file

Issue - State: closed - Opened by kaofishy about 7 years ago - 4 comments

#6 - updated main.cpp

Pull Request - State: closed - Opened by plex1 about 7 years ago - 1 comment

#5 - Compilation error for Briey SoC

Issue - State: closed - Opened by Mani-Sadhasivam about 7 years ago - 2 comments

GitHub / spinalhdl/vexriscv issues and pull requests