Ecosyste.ms: Issues

An open API service for providing issue and pull request metadata for open source projects.

GitHub / spinalhdl/vexriscv issues and pull requests

#442 - Add address granularity for wishbone

Pull Request - State: open - Opened by jdavidberger 5 days ago

#441 - Any way to replace 'Area' with 'Component' in plugin's implementation?

Issue - State: open - Opened by davine47 16 days ago - 5 comments

#440 - Running Regression Test using post_synthesis verilog file

Issue - State: open - Opened by nerdylye 20 days ago - 5 comments

#439 - How to add extra memory to proessor

Issue - State: open - Opened by karegoud 23 days ago - 5 comments

#438 - custom FPU

Issue - State: open - Opened by ztachip 23 days ago - 1 comment

#437 - Regarding the regression test...

Issue - State: open - Opened by nerdylye about 1 month ago - 4 comments

#436 - Do you have plan to add FPU area timing option for vexriscv like vexii?

Issue - State: open - Opened by littlezpf666 about 1 month ago - 2 comments

#435 - Verilog code integration with Murax SOC

Issue - State: closed - Opened by xavier-design about 2 months ago

#434 - add Murax config with native jtag based on the docs

Pull Request - State: closed - Opened by goekce 3 months ago - 3 comments

#433 - Fix undriven signal

Pull Request - State: closed - Opened by 7FM 3 months ago - 3 comments

#432 - Verilator requires at least c++14

Pull Request - State: closed - Opened by goekce 4 months ago - 1 comment

#431 - Verilator expects `-std=c++14`

Issue - State: closed - Opened by goekce 4 months ago - 1 comment

#429 - SiFive GCC link in Readme.md is dead.

Issue - State: closed - Opened by jahagirdar 5 months ago - 1 comment

#428 - What tools are supported

Issue - State: closed - Opened by SeanGan233 5 months ago - 2 comments

#427 - DBusSimplePlugin: don't force SEL to 1111 on read.

Pull Request - State: closed - Opened by kivikakk 5 months ago - 2 comments

#426 - DBusSimplePlugin's Wishbone support forces 32-bit reads

Issue - State: closed - Opened by kivikakk 5 months ago - 3 comments

#425 - build.sbt: Bump SpinalHDL and Scala version

Pull Request - State: closed - Opened by dnltz 5 months ago - 1 comment

#424 - Instruction that need Multiple cycles for execution

Issue - State: closed - Opened by karegoud 5 months ago - 3 comments

#423 - Tunneled EmbeddedRiscvJtag without TAP

Pull Request - State: closed - Opened by craigjb 5 months ago - 1 comment

#422 - Multiple register read from Register file

Issue - State: closed - Opened by xavier-design 6 months ago - 3 comments

#421 - GenFullWithOfficialRiscvDebug failed

Issue - State: closed - Opened by Logiase 6 months ago - 1 comment

#420 - VexRiscv for custom processing in memory instructions

Issue - State: open - Opened by neha2351 6 months ago - 2 comments

#419 - Data buffer

Issue - State: closed - Opened by xavier-design 6 months ago - 6 comments

#418 - new custom instruction in vexriscv

Issue - State: closed - Opened by Chaitanya-kumar-Y 6 months ago - 11 comments

#417 - Add Zkn variant of AES plugin

Pull Request - State: closed - Opened by bunnie 7 months ago - 1 comment

#416 - machineCsr test failing

Issue - State: closed - Opened by jbrown11111 7 months ago - 2 comments

#415 - Internal timer implementation

Issue - State: closed - Opened by juliaazziz 7 months ago - 1 comment

#414 - how to send data serially using apbbus when using murax soc

Issue - State: closed - Opened by karegoud 7 months ago - 4 comments

#413 - Fix Mhz -> MHz in README, comments and Dhrystone benchmark output

Pull Request - State: closed - Opened by mrcmry 8 months ago - 1 comment

#411 - Help for custom instruction

Issue - State: closed - Opened by ztachip 8 months ago - 7 comments

#410 - Exposed write mask on default iBus

Pull Request - State: closed - Opened by MrJake222 8 months ago - 1 comment

#409 - default bus doesn't expose write mask

Issue - State: closed - Opened by MrJake222 8 months ago

#408 - rdcycle and rdinstret instructions not working

Issue - State: closed - Opened by MrJake222 8 months ago - 2 comments

#407 - VexRiscV shift bus fail

Issue - State: closed - Opened by MrJake222 8 months ago - 3 comments

#406 - AxiCrossBar with Standard Axi4 Interface in Briey

Issue - State: open - Opened by ic-hjx 9 months ago - 15 comments

#403 - About the Csr registers in Vexriscv

Issue - State: closed - Opened by ic-hjx 10 months ago - 2 comments

#402 - How to use printf function?

Issue - State: closed - Opened by Guochen-Shine 10 months ago - 10 comments

#401 - Problem about how to compile the software that can be used in Vexriscv with FPU

Issue - State: closed - Opened by ic-hjx 10 months ago - 10 comments

#400 - Problems with adding FPU in Briey

Issue - State: closed - Opened by Guochen-Shine 10 months ago - 5 comments

#399 - Handle `ERR` in `toWishbone`

Pull Request - State: closed - Opened by martijnbastiaan 11 months ago - 2 comments

#398 - Exit cycle accurate simulation

Issue - State: closed - Opened by ashuthosh-mr 11 months ago - 1 comment

#397 - Fix SMP compile-time error when disabling supervisor option

Pull Request - State: closed - Opened by cherrypiejam 11 months ago - 1 comment

#396 - Debug instructions executed twice

Issue - State: closed - Opened by patstew 11 months ago - 5 comments

#395 - Compile C code and run bare metal cycle accurate simulation

Issue - State: open - Opened by nachiket 11 months ago - 3 comments

#394 - Improved the paragraph about available configurations.

Pull Request - State: closed - Opened by PythonLinks 11 months ago - 1 comment

#393 - EU Funding

Issue - State: open - Opened by PythonLinks 11 months ago - 3 comments

#392 - FPU plugin to GenFull.scala

Issue - State: closed - Opened by ashuthosh-mr 11 months ago - 3 comments

#391 - Data Stream in/out SoC <-> FPGA

Issue - State: open - Opened by lk-davidegironi about 1 year ago - 6 comments

#390 - Adding VexRiscV as a dependency

Issue - State: closed - Opened by DanielMadmon about 1 year ago - 2 comments

#388 - Perf counters

Pull Request - State: closed - Opened by jjjt-git about 1 year ago - 9 comments

#387 - Instructions to save/restore register to stack is taking 2 clock each

Issue - State: closed - Opened by ztachip about 1 year ago - 12 comments

#386 - Add mill to compile and test VexRiscv

Pull Request - State: closed - Opened by davine47 about 1 year ago - 1 comment

#384 - debug

Issue - State: open - Opened by chshux about 1 year ago - 1 comment

#383 - Regarding the result of dhrystone with TCM

Issue - State: closed - Opened by piondeno about 1 year ago - 6 comments

#382 - CPU exception signal

Issue - State: closed - Opened by snowprogrammer about 1 year ago - 3 comments

#381 - EmbeddedRiscvJtag synthesis issue

Issue - State: closed - Opened by gregdavill about 1 year ago - 7 comments

#380 - Murax XIP compile issue

Issue - State: open - Opened by lk-davidegironi about 1 year ago - 11 comments

#379 - Transfer data double times

Issue - State: closed - Opened by snowprogrammer about 1 year ago - 1 comment

#378 - Rename `PmpPlugin -> PmpPluginNapot`, `PmpPluginOld -> PmpPlugin`

Pull Request - State: closed - Opened by lschuermann about 1 year ago - 2 comments

#377 - Fix ambiguous function call to bind()

Pull Request - State: closed - Opened by Tectu about 1 year ago - 1 comment

#376 - Combinatorial loop with AhbLite3Decoder

Issue - State: closed - Opened by patstew about 1 year ago - 1 comment

#375 - Add note about Verilator without GDB+OpenOCD

Pull Request - State: closed - Opened by widlarizer over 1 year ago

#374 - PmpPluginOld: fix NAPOT address calculation overflow issue

Pull Request - State: closed - Opened by lschuermann over 1 year ago - 4 comments

#373 - Scratchpad memory with cached IBUS and DBUS?

Issue - State: closed - Opened by piondeno over 1 year ago - 15 comments

#372 - Adding FPU to AHBLite3 config file

Issue - State: closed - Opened by vidushiy25 over 1 year ago - 8 comments

#371 - Assertion when tracing the elaboration issue

Issue - State: closed - Opened by eruanno123 over 1 year ago - 5 comments

#370 - Interface BSCAN2 with VexRiscv's JTAG

Issue - State: closed - Opened by ztachip over 1 year ago - 3 comments

#369 - MAC custom instruction implementation

Issue - State: closed - Opened by Shris7 over 1 year ago - 1 comment

#368 - Read speed: dcache width impact 32bit vs 64bit

Issue - State: closed - Opened by pottendo over 1 year ago - 10 comments

#366 - Add missing parameter jtagHeaderIgnoreWidth

Pull Request - State: closed - Opened by robindust-ce over 1 year ago - 1 comment

#365 - Where are the CLINT and PLIC described?

Issue - State: closed - Opened by PedroAntunes178 over 1 year ago - 5 comments

#364 - Unsupported compressed instruction on VexRiscvAxi4LinuxPlicClint.scala

Issue - State: closed - Opened by PedroAntunes178 over 1 year ago - 3 comments

#363 - VexRiscvAxi4LinuxPlicClint not respecting the AXI protocol

Issue - State: closed - Opened by PedroAntunes178 over 1 year ago - 20 comments

#361 - RiscV Counters

Issue - State: open - Opened by jjjt-git over 1 year ago - 1 comment

#360 - Some documentation on Timer/interrupts

Issue - State: open - Opened by Jupestrone over 1 year ago - 1 comment

#358 - Hi,I have some trouble ,please reply me at your convenience

Issue - State: closed - Opened by siatzjs over 1 year ago - 1 comment

#357 - Dcahce single burst on AXI write

Issue - State: closed - Opened by hszilard13 over 1 year ago - 3 comments

#355 - dev, sim: Error: fpga_spinal.bridge: IR capture error; saw 0x0f not 0x01

Issue - State: open - Opened by likewise over 1 year ago - 3 comments

#354 - How to add I/Dcache support to MURAX

Issue - State: closed - Opened by LongStudy over 1 year ago - 2 comments

#352 - Custom Interruptions error and Selection of the 'A' instruction set

Issue - State: closed - Opened by joeljeanmonod-rgb over 1 year ago - 1 comment

#351 - How can with Murax soc connect a memory on apb bus?

Issue - State: open - Opened by MartinaBarreiroGuerra over 1 year ago - 3 comments

#350 - Add cmd halfPipe function to DBusSimpleBus

Pull Request - State: closed - Opened by AdDraw over 1 year ago - 2 comments

#349 - SIMD_ADD custom instruction not working in C code

Issue - State: closed - Opened by tiagoasilva-meec over 1 year ago - 1 comment

#348 - How the Jtag works when I load the Program?

Issue - State: closed - Opened by xie-1399 over 1 year ago - 1 comment

#347 - Briey on AHBL

Issue - State: closed - Opened by AdDraw over 1 year ago - 6 comments

#346 - Fuzzing VexRiscv

Issue - State: closed - Opened by TobiasKovats over 1 year ago - 6 comments

#342 - How to add a custom instruction that can read rd

Issue - State: closed - Opened by LongStudy over 1 year ago - 8 comments

#333 - Application userspace/hello_world_user in SoC LiteX VexRiscv

Issue - State: closed - Opened by KevinQhv almost 2 years ago - 11 comments