Ecosyste.ms: Issues
An open API service for providing issue and pull request metadata for open source projects.
GitHub / spinalhdl/vexriscv issues and pull requests
#434 - add Murax config with native jtag based on the docs
Pull Request -
State: closed - Opened by goekce 9 days ago
- 3 comments
#433 - Fix undriven signal
Pull Request -
State: closed - Opened by 7FM 11 days ago
- 3 comments
#432 - Verilator requires at least c++14
Pull Request -
State: closed - Opened by goekce about 1 month ago
- 1 comment
#431 - Verilator expects `-std=c++14`
Issue -
State: closed - Opened by goekce about 1 month ago
- 1 comment
#430 - compiling CFU demo configurations results in : java.lang.Exception: Missing inserts : LEGAL_INSTRUCTION"
Issue -
State: closed - Opened by jahagirdar 2 months ago
- 1 comment
#429 - SiFive GCC link in Readme.md is dead.
Issue -
State: closed - Opened by jahagirdar 2 months ago
- 1 comment
#428 - What tools are supported
Issue -
State: closed - Opened by SeanGan233 2 months ago
- 2 comments
#427 - DBusSimplePlugin: don't force SEL to 1111 on read.
Pull Request -
State: closed - Opened by kivikakk 3 months ago
- 2 comments
#426 - DBusSimplePlugin's Wishbone support forces 32-bit reads
Issue -
State: closed - Opened by kivikakk 3 months ago
- 3 comments
#425 - build.sbt: Bump SpinalHDL and Scala version
Pull Request -
State: closed - Opened by dnltz 3 months ago
- 1 comment
#424 - Instruction that need Multiple cycles for execution
Issue -
State: closed - Opened by karegoud 3 months ago
- 3 comments
#423 - Tunneled EmbeddedRiscvJtag without TAP
Pull Request -
State: closed - Opened by craigjb 3 months ago
- 1 comment
#422 - Multiple register read from Register file
Issue -
State: closed - Opened by xavier-design 3 months ago
- 3 comments
#421 - GenFullWithOfficialRiscvDebug failed
Issue -
State: closed - Opened by Logiase 3 months ago
- 1 comment
#420 - VexRiscv for custom processing in memory instructions
Issue -
State: open - Opened by neha2351 4 months ago
- 2 comments
#419 - Data buffer
Issue -
State: closed - Opened by xavier-design 4 months ago
- 6 comments
#418 - new custom instruction in vexriscv
Issue -
State: closed - Opened by Chaitanya-kumar-Y 4 months ago
- 11 comments
#417 - Add Zkn variant of AES plugin
Pull Request -
State: closed - Opened by bunnie 4 months ago
- 1 comment
#416 - machineCsr test failing
Issue -
State: closed - Opened by jbrown11111 5 months ago
- 2 comments
#415 - Internal timer implementation
Issue -
State: closed - Opened by juliaazziz 5 months ago
- 1 comment
#414 - how to send data serially using apbbus when using murax soc
Issue -
State: closed - Opened by karegoud 5 months ago
- 4 comments
#413 - Fix Mhz -> MHz in README, comments and Dhrystone benchmark output
Pull Request -
State: closed - Opened by mrcmry 5 months ago
- 1 comment
#412 - Wrong speculative execution when conditional branch argument is in TCM address range
Issue -
State: closed - Opened by vianney 5 months ago
- 1 comment
#411 - Help for custom instruction
Issue -
State: closed - Opened by ztachip 6 months ago
- 7 comments
#410 - Exposed write mask on default iBus
Pull Request -
State: closed - Opened by MrJake222 6 months ago
- 1 comment
#409 - default bus doesn't expose write mask
Issue -
State: closed - Opened by MrJake222 6 months ago
#408 - rdcycle and rdinstret instructions not working
Issue -
State: closed - Opened by MrJake222 6 months ago
- 2 comments
#407 - VexRiscV shift bus fail
Issue -
State: closed - Opened by MrJake222 6 months ago
- 3 comments
#406 - AxiCrossBar with Standard Axi4 Interface in Briey
Issue -
State: open - Opened by ic-hjx 7 months ago
- 15 comments
#405 - How to only modify certain one reset kind of specific Reg in vex core.
Issue -
State: closed - Opened by littlezpf666 7 months ago
#404 - How to only modify certain one reset kind of specific Reg in vex core.
Issue -
State: open - Opened by littlezpf666 7 months ago
- 1 comment
#403 - About the Csr registers in Vexriscv
Issue -
State: closed - Opened by ic-hjx 7 months ago
- 2 comments
#402 - How to use printf function?
Issue -
State: closed - Opened by Guochen-Shine 7 months ago
- 10 comments
#401 - Problem about how to compile the software that can be used in Vexriscv with FPU
Issue -
State: closed - Opened by ic-hjx 7 months ago
- 10 comments
#400 - Problems with adding FPU in Briey
Issue -
State: closed - Opened by Guochen-Shine 7 months ago
- 5 comments
#399 - Handle `ERR` in `toWishbone`
Pull Request -
State: closed - Opened by martijnbastiaan 8 months ago
- 2 comments
#398 - Exit cycle accurate simulation
Issue -
State: open - Opened by ashuthosh-mr 8 months ago
- 1 comment
#397 - Fix SMP compile-time error when disabling supervisor option
Pull Request -
State: closed - Opened by cherrypiejam 9 months ago
- 1 comment
#396 - Debug instructions executed twice
Issue -
State: closed - Opened by patstew 9 months ago
- 5 comments
#395 - Compile C code and run bare metal cycle accurate simulation
Issue -
State: open - Opened by nachiket 9 months ago
- 3 comments
#394 - Improved the paragraph about available configurations.
Pull Request -
State: closed - Opened by PythonLinks 9 months ago
- 1 comment
#393 - EU Funding
Issue -
State: open - Opened by PythonLinks 9 months ago
- 3 comments
#392 - FPU plugin to GenFull.scala
Issue -
State: closed - Opened by ashuthosh-mr 9 months ago
- 3 comments
#391 - Data Stream in/out SoC <-> FPGA
Issue -
State: open - Opened by lk-davidegironi 10 months ago
- 6 comments
#390 - Adding VexRiscV as a dependency
Issue -
State: closed - Opened by DanielMadmon 10 months ago
- 2 comments
#389 - DE0-Nano Board with VexRiscV: IO and Fit Design Issues Including Specific Command Used
Issue -
State: open - Opened by Tahamermer 10 months ago
- 3 comments
#388 - Perf counters
Pull Request -
State: closed - Opened by jjjt-git 10 months ago
- 9 comments
#387 - Instructions to save/restore register to stack is taking 2 clock each
Issue -
State: closed - Opened by ztachip 10 months ago
- 12 comments
#386 - Add mill to compile and test VexRiscv
Pull Request -
State: closed - Opened by davine47 11 months ago
- 1 comment
#385 - Fetch dosen't performed correctly in the simulation of Murax SOC.(+Custom instructions are executed in unexpected time.)
Issue -
State: open - Opened by nohahanon 11 months ago
- 1 comment
#384 - debug
Issue -
State: open - Opened by chshux 12 months ago
- 1 comment
#383 - Regarding the result of dhrystone with TCM
Issue -
State: closed - Opened by piondeno 12 months ago
- 6 comments
#382 - CPU exception signal
Issue -
State: closed - Opened by snowprogrammer 12 months ago
- 3 comments
#381 - EmbeddedRiscvJtag synthesis issue
Issue -
State: closed - Opened by gregdavill 12 months ago
- 7 comments
#380 - Murax XIP compile issue
Issue -
State: open - Opened by lk-davidegironi 12 months ago
- 11 comments
#379 - Transfer data double times
Issue -
State: closed - Opened by snowprogrammer about 1 year ago
- 1 comment
#378 - Rename `PmpPlugin -> PmpPluginNapot`, `PmpPluginOld -> PmpPlugin`
Pull Request -
State: closed - Opened by lschuermann about 1 year ago
- 2 comments
#377 - Fix ambiguous function call to bind()
Pull Request -
State: closed - Opened by Tectu about 1 year ago
- 1 comment
#376 - Combinatorial loop with AhbLite3Decoder
Issue -
State: closed - Opened by patstew about 1 year ago
- 1 comment
#375 - Add note about Verilator without GDB+OpenOCD
Pull Request -
State: closed - Opened by widlarizer about 1 year ago
#374 - PmpPluginOld: fix NAPOT address calculation overflow issue
Pull Request -
State: closed - Opened by lschuermann about 1 year ago
- 4 comments
#373 - Scratchpad memory with cached IBUS and DBUS?
Issue -
State: closed - Opened by piondeno about 1 year ago
- 15 comments
#372 - Adding FPU to AHBLite3 config file
Issue -
State: closed - Opened by vidushiy25 about 1 year ago
- 8 comments
#371 - Assertion when tracing the elaboration issue
Issue -
State: closed - Opened by eruanno123 about 1 year ago
- 5 comments
#370 - Interface BSCAN2 with VexRiscv's JTAG
Issue -
State: closed - Opened by ztachip about 1 year ago
- 3 comments
#369 - MAC custom instruction implementation
Issue -
State: closed - Opened by Shris7 about 1 year ago
- 1 comment
#368 - Read speed: dcache width impact 32bit vs 64bit
Issue -
State: closed - Opened by pottendo about 1 year ago
- 10 comments
#367 - sbt fail: [error] error while loading <root>, Error accessing... scalactic_2.11-3.2.5.jar
Issue -
State: closed - Opened by pottendo about 1 year ago
- 4 comments
#366 - Add missing parameter jtagHeaderIgnoreWidth
Pull Request -
State: closed - Opened by robindust-ce about 1 year ago
- 1 comment
#365 - Where are the CLINT and PLIC described?
Issue -
State: closed - Opened by PedroAntunes178 about 1 year ago
- 5 comments
#364 - Unsupported compressed instruction on VexRiscvAxi4LinuxPlicClint.scala
Issue -
State: closed - Opened by PedroAntunes178 about 1 year ago
- 3 comments
#363 - VexRiscvAxi4LinuxPlicClint not respecting the AXI protocol
Issue -
State: closed - Opened by PedroAntunes178 about 1 year ago
- 20 comments
#362 - compiling verilog code in verilator by Verilator 4.216 2021-12-05 rev v4.216
Issue -
State: open - Opened by SoCScholar about 1 year ago
- 1 comment
#361 - RiscV Counters
Issue -
State: open - Opened by jjjt-git about 1 year ago
- 1 comment
#360 - Some documentation on Timer/interrupts
Issue -
State: open - Opened by Jupestrone over 1 year ago
- 1 comment
#359 - A bug in https://github.com/SpinalHDL/VexRiscv/blob/master/src/main/scala/vexriscv/plugin/DecoderSimplePlugin.scala
Issue -
State: closed - Opened by FvTao over 1 year ago
- 1 comment
#358 - Hi,I have some trouble ,please reply me at your convenience
Issue -
State: closed - Opened by siatzjs over 1 year ago
- 1 comment
#357 - Dcahce single burst on AXI write
Issue -
State: closed - Opened by hszilard13 over 1 year ago
- 3 comments
#356 - In configuration modified based on briey, the lw instruction cannot access the unaligned address
Issue -
State: closed - Opened by LongStudy over 1 year ago
- 7 comments
#355 - dev, sim: Error: fpga_spinal.bridge: IR capture error; saw 0x0f not 0x01
Issue -
State: open - Opened by likewise over 1 year ago
- 3 comments
#354 - How to add I/Dcache support to MURAX
Issue -
State: closed - Opened by LongStudy over 1 year ago
- 2 comments
#353 - Error running MURAX on ARTY-A7 board and printing characters over Serial Port using println function
Issue -
State: closed - Opened by LongStudy over 1 year ago
- 5 comments
#352 - Custom Interruptions error and Selection of the 'A' instruction set
Issue -
State: closed - Opened by joeljeanmonod-rgb over 1 year ago
- 1 comment
#351 - How can with Murax soc connect a memory on apb bus?
Issue -
State: open - Opened by MartinaBarreiroGuerra over 1 year ago
- 3 comments
#350 - Add cmd halfPipe function to DBusSimpleBus
Pull Request -
State: closed - Opened by AdDraw over 1 year ago
- 2 comments
#349 - SIMD_ADD custom instruction not working in C code
Issue -
State: closed - Opened by tiagoasilva-meec over 1 year ago
- 1 comment
#348 - How the Jtag works when I load the Program?
Issue -
State: closed - Opened by xie-1399 over 1 year ago
- 1 comment
#347 - Briey on AHBL
Issue -
State: closed - Opened by AdDraw over 1 year ago
- 6 comments
#346 - Fuzzing VexRiscv
Issue -
State: closed - Opened by TobiasKovats over 1 year ago
- 6 comments
#342 - How to add a custom instruction that can read rd
Issue -
State: closed - Opened by LongStudy over 1 year ago
- 8 comments
#333 - Application userspace/hello_world_user in SoC LiteX VexRiscv
Issue -
State: closed - Opened by KevinQhv over 1 year ago
- 11 comments
#321 - Bug report: single-precision multiplication or division followed by conversion sets wrong bits in the mantissa
Issue -
State: closed - Opened by flaviens over 1 year ago
- 3 comments
#298 - RISC-V Vector extensions support
Issue -
State: open - Opened by YiminGao0113 almost 2 years ago
- 3 comments
#287 - verilator 5 - simulation failed for Linux.scala
Issue -
State: open - Opened by laurentiuduca almost 2 years ago
- 6 comments
#277 - How to use custom instruction in C code?
Issue -
State: closed - Opened by adz0612 about 2 years ago
- 14 comments
#259 - DataCache Supporting Multiple Cycle RAMs?
Issue -
State: closed - Opened by dockside-code over 2 years ago
- 12 comments
#244 - Adding FPU
Issue -
State: open - Opened by ghost over 2 years ago
- 4 comments
#104 - Ping me if you are waiting a feedback/answer to one of your issues :)
Issue -
State: open - Opened by Dolu1990 almost 5 years ago
- 27 comments
#100 - enable ecall support in small config
Pull Request -
State: closed - Opened by mateusz-holenko almost 5 years ago
- 17 comments
#99 - How can i debug the customInstruction
Issue -
State: closed - Opened by Khaiduy almost 5 years ago
- 12 comments