Data

Tools

Indexes

Applications

Experiments

Issues

An open API service for providing issue and pull request metadata for open source projects.

GitHub / sifive/fpga-shells issues and pull requests

#100 - removing inline tc comment

Pull Request - State: closed - Opened by erikdanie over 5 years ago

#99 - Tcl env var

Pull Request - State: closed - Opened by erikdanie over 5 years ago

#98 - Sdc fix rebase

Pull Request - State: closed - Opened by erikdanie over 5 years ago

#97 - [WIP] device clocks are driven from clockNodes

Pull Request - State: open - Opened by hcook over 5 years ago

#96 - Add extra xdc

Pull Request - State: closed - Opened by erikdanie over 5 years ago

#95 - Bscan rebase

Pull Request - State: closed - Opened by soheil-shababi over 5 years ago - 2 comments

#94 - Add ClockBundle Placed Overlay

Pull Request - State: closed - Opened by rmac-sifive over 5 years ago

#93 - Bscan rebase

Pull Request - State: closed - Opened by erikdanie over 5 years ago

#92 - get files from wake env var

Pull Request - State: closed - Opened by erikdanie over 5 years ago - 1 comment

#91 - -

Issue - State: closed - Opened by minisparrow over 5 years ago

#88 - fix string lieral

Pull Request - State: closed - Opened by erikdanie over 5 years ago

#87 - Fix imports for Chisel 3.2

Pull Request - State: closed - Opened by jackkoenig almost 6 years ago - 1 comment

#86 - Shell rework

Pull Request - State: closed - Opened by erikdanie almost 6 years ago

#85 - Debug: Make Debug Module optional

Pull Request - State: closed - Opened by ernie-sifive almost 6 years ago - 3 comments

#84 - no pullup on keeper pin

Pull Request - State: closed - Opened by erikdanie almost 6 years ago

#83 - Vc707 1 4gb config

Pull Request - State: closed - Opened by erikdanie almost 6 years ago

#82 - Overlays: Analog, change top-level io connectivity

Pull Request - State: closed - Opened by rmac-sifive almost 6 years ago

#81 - Fix vc707+FMC-PCIe do not work after 6094008

Pull Request - State: closed - Opened by mcd500 almost 6 years ago - 3 comments

#80 - Revert "Revert "SPI speedup related FPGA changes""

Pull Request - State: closed - Opened by mcd500 almost 6 years ago - 3 comments

#79 - Vc707 nopcie switchable parant freedom

Pull Request - State: closed - Opened by mcd500 almost 6 years ago - 2 comments

#78 - Trace newshells

Pull Request - State: closed - Opened by ernie-sifive almost 6 years ago

#77 - remove api-generator-sifive dependency

Pull Request - State: open - Opened by albertchen-sifive about 6 years ago

#76 - fixes to ethernet axi4lite device to get compiling

Pull Request - State: closed - Opened by reedafoster about 6 years ago

#75 - change clock domain of island, add fragmenter for axilite

Pull Request - State: closed - Opened by erikdanie about 6 years ago

#74 - remove extra param and add comment

Pull Request - State: closed - Opened by erikdanie about 6 years ago

#73 - Gpio fix

Pull Request - State: closed - Opened by erikdanie about 6 years ago

#72 - Add README for repo

Pull Request - State: closed - Opened by reedafoster about 6 years ago - 1 comment

#71 - Wake

Pull Request - State: closed - Opened by erikdanie about 6 years ago

#70 - Cjtag Overlay/Shell support

Pull Request - State: closed - Opened by erikdanie about 6 years ago

#69 - Fpgashells bump

Pull Request - State: closed - Opened by erikdanie about 6 years ago

#67 - Add tactical String concats to avoid Scala compiler stack overflow

Pull Request - State: closed - Opened by jackkoenig about 6 years ago - 2 comments

#66 - fixing vc707 tcl constraints

Pull Request - State: closed - Opened by erikdanie over 6 years ago

#65 - false path to fix timing

Pull Request - State: closed - Opened by erikdanie over 6 years ago

#64 - Vc707 nopcie switchable

Pull Request - State: closed - Opened by mcd500 over 6 years ago - 12 comments

#63 - Expose JC for trace I/O

Pull Request - State: closed - Opened by ernie-sifive over 6 years ago
Labels: enhancement

#62 - Gpio pmod overlay

Pull Request - State: closed - Opened by erikdanie over 6 years ago

#61 - Correct typos in init.tcl

Pull Request - State: closed - Opened by felixonmars over 6 years ago

#60 - Fix Polarfire compile errors

Pull Request - State: closed - Opened by rmac-sifive over 6 years ago

#59 - VC707: Add ULPI constraints

Pull Request - State: closed - Opened by rmac-sifive over 6 years ago

#58 - Add ULPI constraints for VC707 configs

Pull Request - State: closed - Opened by rmac-sifive over 6 years ago

#57 - Adding Future Avalanche Board design files

Pull Request - State: open - Opened by CLappin over 6 years ago

#56 - Move JTAG to LCD connector

Pull Request - State: closed - Opened by tmagik over 6 years ago - 6 comments

#55 - Qspi newshell

Pull Request - State: closed - Opened by erikdanie over 6 years ago

#54 - updated for libero v12.0

Pull Request - State: closed - Opened by donthus over 6 years ago - 2 comments

#53 - Replace toBool(s) with asBool(s)

Pull Request - State: closed - Opened by jackkoenig over 6 years ago

#52 - Layer VCU118 shell above VCU118ShellBasicOverlays

Pull Request - State: closed - Opened by henrystyles over 6 years ago

#51 - New Arty 100T Shell

Pull Request - State: closed - Opened by erikdanie over 6 years ago

#50 - connectSPI and connectUART no longer require entire dut

Pull Request - State: closed - Opened by hcook over 6 years ago - 2 comments

#49 - XDMA: support ECAM at any legal multiple

Pull Request - State: closed - Opened by terpstra over 6 years ago

#48 - 10G Ethernet

Pull Request - State: closed - Opened by terpstra over 6 years ago

#47 - Fpga spi speedup2

Pull Request - State: closed - Opened by mhtwn over 6 years ago - 1 comment

#46 - Fpga spi speedup

Pull Request - State: closed - Opened by mhtwn almost 7 years ago - 1 comment
Labels: enhancement

#45 - Revert "Fpga spi speedup"

Pull Request - State: closed - Opened by mwachs5 almost 7 years ago

#44 - mbus: switch to multi-bank API

Pull Request - State: closed - Opened by terpstra almost 7 years ago

#43 - Fpga spi speedup

Pull Request - State: closed - Opened by mhtwn almost 7 years ago

#42 - Xilinx: Add KEEPER primitive

Pull Request - State: closed - Opened by mwachs5 almost 7 years ago

#41 - Make some of the connector methods more flexible

Pull Request - State: open - Opened by mwachs5 almost 7 years ago - 1 comment

#40 - VC707Shell: default to 1GB of RAM (what the board ships with)

Pull Request - State: closed - Opened by terpstra almost 7 years ago

#39 - IO Overlays: use AttachParams

Pull Request - State: closed - Opened by hcook almost 7 years ago

#38 - Renamed arty-a7-100 to arty_a7_100. BOARD

Pull Request - State: closed - Opened by RajeshVaradharajan almost 7 years ago

#37 - Added arty-a7-100 board

Pull Request - State: closed - Opened by RajeshVaradharajan almost 7 years ago

#36 - vcu118: make it possible to instantiate two PCIe interfaces at once

Pull Request - State: closed - Opened by terpstra almost 7 years ago

#35 - VCU118 PCIe gen3 x4 + x8

Pull Request - State: closed - Opened by terpstra almost 7 years ago

#34 - Shell Design Refactoring Enhancements

Pull Request - State: closed - Opened by sagark almost 7 years ago

#33 - BundleBridge: use source and sink nodes directly

Pull Request - State: closed - Opened by hcook about 7 years ago - 1 comment

#32 - ClockCrossingType: fix bad merge

Pull Request - State: closed - Opened by hcook about 7 years ago

#31 - crossinghelper: minimal compliance with new API

Pull Request - State: closed - Opened by hcook about 7 years ago

#30 - VC707: fix legacy Shell

Pull Request - State: closed - Opened by terpstra about 7 years ago

#29 - Make 2.12 type checker happy

Pull Request - State: closed - Opened by jackkoenig about 7 years ago

#28 - Shell-Design Split

Pull Request - State: closed - Opened by terpstra about 7 years ago

#27 - Make MIG clocking internal and clean-up MMCM code style

Pull Request - State: closed - Opened by terpstra about 7 years ago

#26 - VCU118 support

Pull Request - State: closed - Opened by farzadfch about 7 years ago

#25 - Wip diplomatic pll

Pull Request - State: closed - Opened by terpstra about 7 years ago
Labels: help wanted

#24 - VC707PCIe: adapt to AXI4Lite API change

Pull Request - State: closed - Opened by terpstra about 7 years ago

#23 - Clock consolidation

Pull Request - State: closed - Opened by zaddan about 7 years ago - 1 comment

#22 - Microsemi rebased

Pull Request - State: closed - Opened by zaddan about 7 years ago - 3 comments

#21 - Add JTAG TCK clock constraint to VC707

Pull Request - State: closed - Opened by mwachs5 about 7 years ago

#20 - chiplink: add pinout

Pull Request - State: closed - Opened by terpstra over 7 years ago

#19 - VCU118 Support

Pull Request - State: closed - Opened by farzadfch over 7 years ago

#18 - Dynamic clock groups

Pull Request - State: closed - Opened by terpstra over 7 years ago

#17 - periphery: bus api update

Pull Request - State: closed - Opened by hcook over 7 years ago

#16 - Chiplink 100

Pull Request - State: closed - Opened by terpstra over 7 years ago - 1 comment

#15 - TransferSizes: just because a device CAN do more does not mean it should

Pull Request - State: closed - Opened by terpstra over 7 years ago

#13 - xilinxvc707pciex1: use new node-style API and abstract crossing

Pull Request - State: closed - Opened by terpstra almost 8 years ago

#12 - xilinxVC707mig: convert to the island pattern

Pull Request - State: closed - Opened by terpstra almost 8 years ago

#11 - VC707 use IP IO bundles

Pull Request - State: closed - Opened by henrystyles almost 8 years ago

#10 - TLToAXI4: remove now unnecessary argument

Pull Request - State: closed - Opened by terpstra almost 8 years ago

#9 - Allow additional constraints directory to be provided

Pull Request - State: closed - Opened by mwachs5 almost 8 years ago - 4 comments

#8 - Restructure Tcl script entrypoint.

Pull Request - State: closed - Opened by richardxia almost 8 years ago - 1 comment

#7 - diplomacy: update to new API

Pull Request - State: closed - Opened by terpstra almost 8 years ago

#6 - signal_bundles: Use the new way as .fromPorts is gone

Pull Request - State: closed - Opened by mwachs5 almost 8 years ago

#5 - Use a file instead of environment variable to pass VSRCS into Vivado

Pull Request - State: closed - Opened by henrystyles almost 8 years ago

#4 - Support both 4G and 1GB DIMM configuration for VC707

Pull Request - State: closed - Opened by henrystyles almost 8 years ago

#3 - fix PCIe vc707 design contraints : PCIe pins and UART RX sync register

Pull Request - State: closed - Opened by henrystyles almost 8 years ago

#2 - Arty: Allow a slower core clk

Pull Request - State: open - Opened by mwachs5 almost 8 years ago

#1 - synchronizers: Use new primitives

Pull Request - State: closed - Opened by mwachs5 almost 8 years ago