Ecosyste.ms: Issues

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GitHub / sifive/duh issues and pull requests

#91 - relax validation

Issue - State: open - Opened by mrwinsto about 1 year ago

#90 - repetitive sets of items

Issue - State: open - Opened by drom about 1 year ago

#89 - duh status command

Pull Request - State: open - Opened by adeelliaquat-lm almost 4 years ago

#88 - Install SuiteSparse header files during CI

Pull Request - State: closed - Opened by seldridge about 4 years ago

#87 - DuH validate not handling verbose port definitions

Issue - State: open - Opened by seldridge about 4 years ago

#86 - DuH Validate Returns Zero Exit Code on Validation Failure

Issue - State: open - Opened by seldridge about 4 years ago - 1 comment

#85 - Design option in "Block Type" doesn't create any (.json5) base document

Issue - State: open - Opened by adeelliaquat-lm about 4 years ago - 2 comments
Labels: bug

#83 - No module named 'cvxopt'

Issue - State: closed - Opened by davidmlw about 4 years ago - 1 comment

#82 - fixes #66

Pull Request - State: closed - Opened by Ramlakshmi3733 about 4 years ago

#81 - duh validate doesn't work with absolute paths.

Issue - State: closed - Opened by rpadler about 4 years ago - 3 comments

#80 - Default value of access/modifiedWriteValue/readAction properties

Issue - State: closed - Opened by taichi-ishitani over 4 years ago - 2 comments

#79 - replace master/slave -> initiator/target

Issue - State: open - Opened by drom over 4 years ago - 1 comment

#78 - duh validate should disallow duplicate address block names

Issue - State: closed - Opened by richardxia over 4 years ago - 3 comments

#77 - "component" is spelled wrong in validate command

Issue - State: closed - Opened by mwachs5 over 4 years ago

#75 - detect type of the document

Issue - State: open - Opened by drom over 4 years ago

#74 - component, busInterface, portMap, port concatenation

Issue - State: closed - Opened by drom over 4 years ago
Labels: enhancement

#73 - warning about unmapped ports (component)

Issue - State: open - Opened by drom over 4 years ago
Labels: enhancement

#72 - duh validate issues a warning on bundles

Issue - State: closed - Opened by Ramlakshmi3733 over 4 years ago - 1 comment
Labels: bug

#70 - duh get the root document

Issue - State: closed - Opened by drom over 4 years ago

#69 - use duh-core

Issue - State: closed - Opened by drom over 4 years ago

#67 - report status of DUH document

Issue - State: open - Opened by drom almost 5 years ago - 10 comments

#66 - duh validate prints out unnecessary validation errors when DUH document not passed in

Issue - State: closed - Opened by richardxia almost 5 years ago - 2 comments
Labels: bug

#65 - https://duh.run website broken

Issue - State: closed - Opened by mithro almost 5 years ago - 3 comments
Labels: enhancement

#63 - cascading attributes: memoryMap -> register -> field

Issue - State: open - Opened by drom almost 5 years ago

#62 - Fetch $ref files

Issue - State: closed - Opened by drom almost 5 years ago

#60 - duh validate returns 0 even if error is found

Issue - State: closed - Opened by jackkoenig almost 5 years ago

#59 - duh validate doesn't find custom buses

Issue - State: open - Opened by olofk about 5 years ago - 2 comments

#58 - inout verilog import - width missing

Issue - State: closed - Opened by drom about 5 years ago - 4 comments

#57 - CLIi to validate parameters against component parameter schema

Issue - State: open - Opened by drom about 5 years ago
Labels: enhancement

#56 - Create a Python library for working with DUH?

Issue - State: open - Opened by mithro about 5 years ago - 4 comments

#55 - duh-design

Issue - State: open - Opened by hiren-99 over 5 years ago

#53 - import IP-XACT ports and SYSTEMRTL ports

Issue - State: closed - Opened by hiren-99 over 5 years ago - 1 comment

#52 - Import memory map of verilog to json5.

Issue - State: open - Opened by hiren-99 over 5 years ago

#51 - duh-import-verilog-ports isuue

Issue - State: closed - Opened by hiren-99 over 5 years ago - 3 comments

#49 - validate port interfaces mapped to existing ports

Issue - State: closed - Opened by drom over 5 years ago

#48 - Validate Bus Interfaces against Bus Definitions

Issue - State: closed - Opened by drom over 5 years ago

#47 - Duh import verilog ports issue

Issue - State: closed - Opened by v-krvavac over 5 years ago - 3 comments
Labels: question

#46 - Remove wake rules, they're out of date anyway

Pull Request - State: closed - Opened by jackkoenig over 5 years ago

#40 - Can't map parts of signals in duh

Issue - State: open - Opened by v-krvavac over 5 years ago
Labels: enhancement

#36 - Travis CI failing on Windows

Issue - State: open - Opened by drom over 5 years ago

#35 - Travis CI failing on OSX

Issue - State: open - Opened by drom over 5 years ago

#34 - Create LICENSE

Pull Request - State: closed - Opened by drom over 5 years ago

#33 - tick-define macro substituted with incorrect value in json5

Issue - State: open - Opened by ghost over 5 years ago - 1 comment
Labels: bug

#31 - verilog macro flagged as syntax error

Issue - State: closed - Opened by ghost over 5 years ago - 5 comments
Labels: invalid

#30 - pinlist empty if blank line after module module_name (

Issue - State: closed - Opened by ghost over 5 years ago - 3 comments

#28 - Issue in importing verilog ports to json5

Issue - State: closed - Opened by sidharth94 over 5 years ago - 2 comments

#27 - clean all unused references in the definition section

Issue - State: open - Opened by drom over 5 years ago - 1 comment

#26 - duh-export-verilog-bbx CLI

Issue - State: closed - Opened by drom over 5 years ago

#24 - use duh schema from duh-schema

Issue - State: closed - Opened by drom almost 6 years ago - 2 comments

#23 - Verilog to json5

Issue - State: closed - Opened by shiviarorasifive almost 6 years ago - 3 comments

#22 - How is mycom-busprop.json supposed to be interpreted/used?

Issue - State: closed - Opened by ghost almost 6 years ago - 1 comment

#21 - provide better error message when verilog pinlist import fails

Issue - State: closed - Opened by drom almost 6 years ago

#19 - added duhportinf as a dependency

Pull Request - State: closed - Opened by abishara almost 6 years ago

#18 - infer-channels

Issue - State: closed - Opened by drom almost 6 years ago - 1 comment

#16 - Verilog integration

Issue - State: open - Opened by drom almost 6 years ago
Labels: import, export

#15 - SystemRDL integration

Issue - State: open - Opened by drom almost 6 years ago
Labels: registers, import, export

#14 - get command

Issue - State: closed - Opened by drom almost 6 years ago

#13 - generate Scala wrapper for Scala / Chisel designed blocks

Issue - State: closed - Opened by drom almost 6 years ago - 1 comment

#12 - display Test coverage report

Issue - State: closed - Opened by drom almost 6 years ago

#11 - display Verilator code coverage report

Issue - State: open - Opened by drom almost 6 years ago

#9 - support logicalTieOff in portMap

Issue - State: open - Opened by drom about 6 years ago
Labels: enhancement

#8 - user parameter schema

Issue - State: open - Opened by drom about 6 years ago
Labels: enhancement

#7 - add clock / reset definition

Issue - State: open - Opened by drom about 6 years ago
Labels: enhancement

#6 - generate editable Datasheet from component schema and config

Issue - State: open - Opened by drom about 6 years ago
Labels: enhancement

#5 - component CSR section

Issue - State: closed - Opened by drom about 6 years ago
Labels: enhancement

#4 - Verilog black box generator

Issue - State: closed - Opened by drom about 6 years ago
Labels: enhancement

#2 - add scaffolding generator

Issue - State: closed - Opened by drom about 6 years ago - 1 comment
Labels: enhancement

#1 - add component spec schema

Issue - State: closed - Opened by drom about 6 years ago
Labels: enhancement