sifive/duh-scala issues and pull requests

#83 - BundleBridgeSource/Sink need ()

Issue - State: closed - Opened by mwachs5 over 4 years ago - 1 comment

#82 - label emitted scala files with duh-scala version number

Issue - State: open - Opened by mwachs5 over 4 years ago - 5 comments

#81 - fix to emit correct INTERRUPT code

Pull Request - State: closed - Opened by drom over 4 years ago - 1 comment

#80 - work towards #79 ; multiple address blocks and the emitted Object Model

Pull Request - State: closed - Opened by drom over 4 years ago - 2 comments

#79 - What should the behavior of duh-export-scala be with respect to multiple address blocks and the emitted Object Model?

Issue - State: closed - Opened by richardxia over 4 years ago - 28 comments

#78 - duh-scala/rocket-chip CLI flow does not work with module with underscore in name

Issue - State: closed - Opened by richardxia over 4 years ago - 9 comments

#77 - Properly set the resources on the APBSlaveParameters.

Pull Request - State: closed - Opened by richardxia over 4 years ago - 2 comments

#76 - Diplomacy APBSlaveNode is missing resources argument; results in missing OMMemoryRegions

Issue - State: closed - Opened by richardxia over 4 years ago

#75 - read DUH in Scala

Issue - State: open - Opened by drom over 4 years ago - 2 comments

#74 - support native TileLink ports.

Issue - State: open - Opened by drom over 4 years ago

#73 - use duh-bus definitions where possible

Issue - State: open - Opened by drom over 4 years ago

#72 - Handle unsorted register fields

Pull Request - State: closed - Opened by richardxia over 4 years ago - 1 comment

#71 - Interrupt is not implemented after 'duh-export-scala'

Issue - State: open - Opened by RyanSangdeokPark over 4 years ago

#70 - Support for AMBA3 APB

Issue - State: closed - Opened by drom over 4 years ago

#69 - Allow for newline characters in register description.

Pull Request - State: closed - Opened by richardxia over 4 years ago

#68 - Support multiline string descriptions for registers

Issue - State: closed - Opened by richardxia over 4 years ago

#67 - Support for AXI-Stream

Issue - State: open - Opened by drom almost 5 years ago

#66 - Replace .asOutput with Output() for chisel3 forwards compatibility.

Pull Request - State: closed - Opened by richardxia almost 5 years ago

#65 - Don't overpad fields by accounting for width.

Pull Request - State: closed - Opened by richardxia almost 5 years ago - 1 comment

#64 - Validation errors in CLI output are confusing

Issue - State: closed - Opened by richardxia almost 5 years ago - 2 comments

#63 - make dpram/spram chisel attch code overrideable

Pull Request - State: open - Opened by albertchen-sifive almost 5 years ago

#62 - add TLFIFOFixer to AXI4Master adapter chain

Pull Request - State: closed - Opened by albertchen-sifive almost 5 years ago

#61 - added support for maxBurst

Pull Request - State: closed - Opened by drom almost 5 years ago

#60 - Error out if blackbox port doesn't match bus definition.

Pull Request - State: closed - Opened by richardxia almost 5 years ago - 2 comments

#59 - Fix APB port directions

Pull Request - State: closed - Opened by richardxia almost 5 years ago

#58 - fix chisel types and directions for analog signals

Pull Request - State: closed - Opened by albertchen-sifive almost 5 years ago

#57 - refactor scala codegen into separate NPM package

Issue - State: open - Opened by drom almost 5 years ago

#56 - fixes #55 ; validate input files at the beginning.

Pull Request - State: closed - Opened by drom almost 5 years ago

#55 - Validate input files at the beginning

Issue - State: closed - Opened by richardxia almost 5 years ago - 1 comment
Labels: bug

#54 - enable exclusion of bus fields that are not defined in rocket-chip

Pull Request - State: closed - Opened by albertchen-sifive almost 5 years ago

#53 - regmap: fix port connections, fix RegField wires

Pull Request - State: closed - Opened by albertchen-sifive almost 5 years ago

#52 - Set resetValue in OMRegFieldDesc if present.

Pull Request - State: closed - Opened by richardxia almost 5 years ago

#51 - use def instead of val for desiredName override

Pull Request - State: closed - Opened by albertchen-sifive almost 5 years ago - 2 comments

#50 - add support for addressUnitBits field

Pull Request - State: closed - Opened by albertchen-sifive almost 5 years ago

#49 - update export-scala-regmap for duh-schema 0.7.1

Pull Request - State: closed - Opened by albertchen-sifive almost 5 years ago

#48 - use endent for code blocks, cleanup

Pull Request - State: closed - Opened by albertchen-sifive almost 5 years ago

#47 - add duh-export-regmap/monitor to package.json bin

Pull Request - State: closed - Opened by albertchen-sifive almost 5 years ago

#46 - rename AXI4Lite to AXI4-Lite

Pull Request - State: closed - Opened by albertchen-sifive almost 5 years ago

#45 - use bus direction when connecting bus ports

Pull Request - State: closed - Opened by albertchen-sifive almost 5 years ago

#44 - make OM mems/ints overrideable, add OMRegisterMaps

Pull Request - State: closed - Opened by albertchen-sifive almost 5 years ago

#43 - address feedback on README.md

Pull Request - State: closed - Opened by albertchen-sifive almost 5 years ago

#42 - fix AXI4-Lite typo

Pull Request - State: closed - Opened by albertchen-sifive almost 5 years ago

#41 - duh-export-scala

Issue - State: open - Opened by hiren-99 about 5 years ago

#40 - document generated Scala API

Pull Request - State: closed - Opened by albertchen-sifive almost 5 years ago - 1 comment

#39 - add export-scala-monitor

Pull Request - State: closed - Opened by albertchen-sifive almost 5 years ago - 2 comments

#38 - APB: fix AddressSet mask

Pull Request - State: closed - Opened by albertchen-sifive about 5 years ago

#37 - error on using inout in json5 while exporting scala

Issue - State: closed - Opened by ghost about 5 years ago - 5 comments
Labels: bug

#36 - emit 'exists' ResourceBinding in base scala

Pull Request - State: closed - Opened by albertchen-sifive about 5 years ago - 1 comment

#35 - Memories clocking

Issue - State: closed - Opened by v-krvavac about 5 years ago - 6 comments

#34 - AXI signals visibility for monitoring

Issue - State: closed - Opened by v-krvavac about 5 years ago - 1 comment

#33 - add attach for LogicalTreeNode

Pull Request - State: closed - Opened by albertchen-sifive about 5 years ago - 1 comment

#32 - Fragmenter value for APBtoTL

Issue - State: closed - Opened by v-krvavac about 5 years ago - 5 comments

#31 - wrong parameter passed to `TLWidthWidget` of axi slave node attach

Issue - State: open - Opened by albertchen-sifive about 5 years ago - 2 comments

#30 - add resource bindings and LogicalTreeNode/OM hooks

Pull Request - State: closed - Opened by albertchen-sifive about 5 years ago

#29 - add export-scala-regmap

Pull Request - State: closed - Opened by albertchen-sifive about 5 years ago - 2 comments

#28 - fix connections for portMaps with mixed case

Pull Request - State: open - Opened by albertchen-sifive about 5 years ago - 2 comments

#27 - support setting clocks for spram/dpram

Pull Request - State: closed - Opened by albertchen-sifive about 5 years ago

#26 - add support for analog in/out/inout

Pull Request - State: closed - Opened by albertchen-sifive about 5 years ago - 1 comment

#25 - tl2apb has no apb select signal

Issue - State: closed - Opened by v-krvavac about 5 years ago - 1 comment
Labels: bug

#24 - add defaults only if there are adapters

Pull Request - State: closed - Opened by albertchen-sifive about 5 years ago

#23 - implement apb attach functions, fix beatBytes param

Pull Request - State: closed - Opened by albertchen-sifive about 5 years ago

#22 - fix dpram and spram nodes

Pull Request - State: closed - Opened by albertchen-sifive about 5 years ago

#21 - fix bundle bridge nodes

Pull Request - State: closed - Opened by albertchen-sifive about 5 years ago

#20 - make TL adapters optional, delete trailing whitespace

Pull Request - State: closed - Opened by albertchen-sifive over 5 years ago - 1 comment

#19 - TL Fragmenter error in APB Node

Issue - State: closed - Opened by v-krvavac over 5 years ago - 1 comment

#18 - component <-> component bus interface connection without TL adapter

Issue - State: closed - Opened by drom over 5 years ago - 1 comment

#17 - AXI4 slave node adapter address range is frong

Issue - State: closed - Opened by drom over 5 years ago

#16 - run scala output validation when --validate flag is set

Issue - State: closed - Opened by drom over 5 years ago

#15 - APBSlaveNode is not generated

Issue - State: closed - Opened by v-krvavac over 5 years ago - 2 comments
Labels: bug

#14 - Upper case characters error when compiling Scala

Issue - State: closed - Opened by v-krvavac over 5 years ago - 1 comment
Labels: bug

#12 - Minor issues with scala memory generation

Issue - State: closed - Opened by v-krvavac over 5 years ago - 1 comment
Labels: bug

#10 - fix num param and attach names for intc-tl

Pull Request - State: closed - Opened by albertchen-sifive over 5 years ago

#9 - wrong coupling of AXI master node to pbus

Issue - State: closed - Opened by jordiflor over 5 years ago - 2 comments
Labels: bug

GitHub / sifive/duh-scala issues and pull requests