Ecosyste.ms: Issues

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GitHub / rowang077/clash-ethernet issues and pull requests

#29 - Overdragen repository

Issue - State: closed - Opened by lmbollen 10 months ago - 5 comments

#28 - Sending dynamic Ethernet frames

Pull Request - State: open - Opened by syberant over 1 year ago

#27 - Refactor TX side to use clash-protocols + general framework

Pull Request - State: open - Opened by syberant over 1 year ago - 1 comment

#26 - Add clash-protocols as dependency and refactor RGMII

Pull Request - State: closed - Opened by syberant over 1 year ago - 1 comment

#25 - Fixed backslashes in pll125

Pull Request - State: closed - Opened by samuelpadron over 1 year ago - 4 comments

#24 - Fix 125Hz pll primitive

Issue - State: closed - Opened by samuelpadron over 1 year ago

#23 - Made separate pll125 primitive

Pull Request - State: closed - Opened by samuelpadron over 1 year ago

#22 - Crc calculation

Pull Request - State: open - Opened by ThomasB013 over 1 year ago - 3 comments

#21 - 18 move rgmii to clash protocols

Pull Request - State: closed - Opened by syberant over 1 year ago - 4 comments

#19 - 8 rgmii

Pull Request - State: closed - Opened by samuelpadron over 1 year ago - 4 comments

#19 - 8 rgmii

Pull Request - State: closed - Opened by samuelpadron over 1 year ago - 4 comments

#18 - Move RGMII to clash protocols

Issue - State: open - Opened by marcosousapoza over 1 year ago

#16 - Send MAC address target messages. (BC for FPGA)

Pull Request - State: closed - Opened by ThomasB013 over 1 year ago - 2 comments

#15 - Core verifies the checksum of received ethernet frames

Issue - State: open - Opened by syberant over 1 year ago - 2 comments

#14 - Core can send dynamic ethernet frames

Issue - State: open - Opened by syberant over 1 year ago

#13 - Add `delayg`, add initial value to `delayf`

Pull Request - State: closed - Opened by syberant over 1 year ago - 1 comment

#13 - Add `delayg`, add initial value to `delayf`

Pull Request - State: closed - Opened by syberant over 1 year ago - 1 comment

#11 - iddrx1f implementation

Pull Request - State: closed - Opened by marcosousapoza over 1 year ago - 16 comments

#11 - iddrx1f implementation

Pull Request - State: closed - Opened by marcosousapoza over 1 year ago - 16 comments

#10 - Bridge refactor

Pull Request - State: closed - Opened by marcosousapoza over 1 year ago - 1 comment

#9 - Implement Clock Domain Crossing (CDC)

Issue - State: closed - Opened by marcosousapoza over 1 year ago - 3 comments

#8 - RGMII PoC

Issue - State: closed - Opened by marcosousapoza over 1 year ago - 3 comments

#8 - RGMII PoC

Issue - State: closed - Opened by marcosousapoza over 1 year ago - 3 comments

#7 - Create 125Hz pll primitive

Issue - State: closed - Opened by marcosousapoza over 1 year ago - 3 comments

#6 - Split inputs and outputs of topEntity into data types

Pull Request - State: closed - Opened by samuelpadron over 1 year ago - 5 comments

#4 - QBL-RM01 - Implement iddrx1f primitive

Issue - State: closed - Opened by syberant over 1 year ago

#4 - QBL-RM01 - Implement iddrx1f primitive

Issue - State: closed - Opened by syberant over 1 year ago

#3 - Add a UART to MDIO bridge

Pull Request - State: closed - Opened by syberant almost 2 years ago - 16 comments

#3 - Add a UART to MDIO bridge

Pull Request - State: closed - Opened by syberant almost 2 years ago - 16 comments

#2 - UART to MDIO bridge

Issue - State: closed - Opened by marcosousapoza almost 2 years ago - 12 comments

#2 - UART to MDIO bridge

Issue - State: closed - Opened by marcosousapoza almost 2 years ago - 12 comments

#1 - Tracking issue: Getting to a MVP

Issue - State: closed - Opened by syberant almost 2 years ago - 2 comments

#1 - Tracking issue: Getting to a MVP

Issue - State: closed - Opened by syberant almost 2 years ago - 2 comments