Ecosyste.ms: Issues

An open API service for providing issue and pull request metadata for open source projects.

GitHub / rj45/digilogic issues and pull requests

#48 - Remove clone on copy type: `BrushRef`

Pull Request - State: closed - Opened by waywardmonkeys 4 months ago

#47 - Improve some Markdown

Pull Request - State: closed - Opened by waywardmonkeys 4 months ago

#46 - Update to Vello 0.3, egui 0.29, wgpu 22.

Pull Request - State: closed - Opened by waywardmonkeys 4 months ago

#45 - Fix typos

Pull Request - State: closed - Opened by waywardmonkeys 4 months ago - 3 comments

#44 - Added basic circuitfile support

Pull Request - State: closed - Opened by KennethWilke 7 months ago

#43 - New data backend

Pull Request - State: closed - Opened by rj45 8 months ago

#40 - zig 0.13 fixes

Pull Request - State: closed - Opened by bcrist 8 months ago

#39 - Fix windows zig build where project path contains spaces

Pull Request - State: closed - Opened by bcrist 9 months ago

#38 - Use x86_64-windows-gnu by default on windows

Pull Request - State: closed - Opened by bcrist 9 months ago

#37 - Add `zig build cdb`, adjust default windows target for zig

Pull Request - State: closed - Opened by bcrist 9 months ago

#35 - [FEAT/BUG] Component name (gate number) should be reused

Issue - State: open - Opened by rj45 9 months ago

#33 - LazyPath.path is deprecated, Use Build.path() instead

Pull Request - State: closed - Opened by bcrist 9 months ago

#32 - Added grid

Pull Request - State: closed - Opened by rj45 over 2 years ago

#31 - grid dots / lines

Issue - State: closed - Opened by rj45 over 2 years ago

#30 - Add pancam for pan / zoom

Pull Request - State: closed - Opened by rj45 over 2 years ago

#29 - infinite pan via mouse dragging

Issue - State: closed - Opened by rj45 over 2 years ago

#28 - scroll wheel zoom

Issue - State: closed - Opened by rj45 over 2 years ago

#27 - Hellorld!

Pull Request - State: closed - Opened by rj45 over 2 years ago

#26 - bevy hellorld

Issue - State: closed - Opened by rj45 over 2 years ago

#25 - Encourage longer naming of wires and components

Issue - State: closed - Opened by rj45 over 2 years ago

#24 - Split screen viewing multiple circuits at once

Issue - State: closed - Opened by rj45 over 2 years ago

#23 - Tabs for subcircuits

Issue - State: closed - Opened by rj45 over 2 years ago

#22 - Yosys compatible json export

Issue - State: closed - Opened by rj45 over 2 years ago

#21 - Bit-width inference

Issue - State: closed - Opened by rj45 over 2 years ago

#20 - iverilog simulated subcircuits

Issue - State: closed - Opened by rj45 over 2 years ago

#19 - Configurable memories

Issue - State: closed - Opened by rj45 over 2 years ago

#18 - Substitute subcircuits for functional model during simulation

Issue - State: closed - Opened by rj45 over 2 years ago

#17 - Quartz generation / export

Issue - State: closed - Opened by rj45 over 2 years ago

#16 - Verilog generation / export

Issue - State: closed - Opened by rj45 over 2 years ago

#15 - Quartz import / sync support

Issue - State: closed - Opened by rj45 over 2 years ago

#14 - yosys json import

Issue - State: closed - Opened by rj45 over 2 years ago

#13 - Wire bundles for bundling wires together

Issue - State: closed - Opened by rj45 over 2 years ago

#12 - Hideable, colour coded layers for wires and components

Issue - State: closed - Opened by rj45 over 2 years ago

#11 - FST output support

Issue - State: closed - Opened by rj45 over 2 years ago

#10 - VCD output during simulation

Issue - State: closed - Opened by rj45 over 2 years ago

#9 - KiCAD schematic sync / reimport

Issue - State: closed - Opened by rj45 over 2 years ago

#8 - Import KiCAD schematics

Issue - State: closed - Opened by rj45 over 2 years ago

#7 - Import circuits from Digital

Issue - State: closed - Opened by rj45 over 2 years ago

#6 - Timing reports and critical path analysis

Issue - State: closed - Opened by rj45 over 2 years ago

#5 - Support optional simulation of propagation delays

Issue - State: closed - Opened by rj45 over 2 years ago

#4 - Unidirectional ports error if driven the wrong direction

Issue - State: closed - Opened by rj45 over 2 years ago

#3 - Viewing subcircuits while simulation is running

Issue - State: closed - Opened by rj45 over 2 years ago

#2 - Bidirectional inout ports

Issue - State: closed - Opened by rj45 over 2 years ago

#1 - KiCAD netlist sync

Issue - State: closed - Opened by rj45 over 2 years ago - 2 comments