Ecosyste.ms: Issues
An open API service for providing issue and pull request metadata for open source projects.
GitHub / rcore-os/trapframe-rs issues and pull requests
#15 - Clear `DF` flag to conform to x86-64 calling convention
Issue -
State: open - Opened by tangruize 3 months ago
#14 - x86_64: avoid accessing MSR registers when do trap/syscall
Pull Request -
State: closed - Opened by cqs21 8 months ago
#13 - RISC-V Vectored-Mode Trap Entry Support?
Issue -
State: open - Opened by Coekjan over 1 year ago
#12 - Should this library save/restore floating-point registers?
Issue -
State: open - Opened by Coekjan over 1 year ago
#11 - fix examples and publish as v0.9.0
Pull Request -
State: closed - Opened by wangrunji0408 almost 3 years ago
#10 - Fix asm and global_asm macros
Pull Request -
State: closed - Opened by simonschoening about 3 years ago
- 2 comments
#9 - x86_64/gdt.rs panicked at 'attempt to create unaligned or null slice'
Issue -
State: open - Opened by elliott10 about 3 years ago
- 1 comment
#8 - update x86_64 version up to 0.14 in Cargo.toml for newer rustc(1.54+)
Pull Request -
State: closed - Opened by chyyuu over 3 years ago
#7 - Fix build on latest nightly.
Pull Request -
State: closed - Opened by waywardmonkeys about 4 years ago
- 3 comments
Labels: bug
#6 - Enable user space INT 3 and INTO
Pull Request -
State: closed - Opened by benpigchu over 4 years ago
Labels: enhancement
#5 - x86: Support ioports.
Pull Request -
State: closed - Opened by Hoblovski over 4 years ago
Labels: enhancement
#4 - Implement get_sp for UserContext
Pull Request -
State: closed - Opened by jiegec over 4 years ago
#3 - Remove riscv crate and add align for trap_entry
Pull Request -
State: closed - Opened by jiegec over 4 years ago
#2 - Add support for riscv and aarch64
Pull Request -
State: closed - Opened by jiegec over 4 years ago
#1 - Improve general regs
Pull Request -
State: closed - Opened by jiegec over 4 years ago