Ecosyste.ms: Issues

An open API service for providing issue and pull request metadata for open source projects.

GitHub / project-oak/silveroak issues and pull requests

#100 - Implement and test LUT5

Pull Request - State: closed - Opened by satnam6502 over 4 years ago - 1 comment

#100 - Implement and test LUT5

Pull Request - State: closed - Opened by satnam6502 over 4 years ago - 1 comment

#99 - Switch LUT tests to also use Verilator via xeclib rather than unisims

Pull Request - State: closed - Opened by satnam6502 over 4 years ago - 1 comment

#99 - Switch LUT tests to also use Verilator via xeclib rather than unisims

Pull Request - State: closed - Opened by satnam6502 over 4 years ago - 1 comment

#98 - Implement and test LUT4

Pull Request - State: closed - Opened by satnam6502 over 4 years ago - 1 comment

#98 - Implement and test LUT4

Pull Request - State: closed - Opened by satnam6502 over 4 years ago - 1 comment

#97 - Implement and test LUT3

Pull Request - State: closed - Opened by satnam6502 over 4 years ago - 1 comment

#97 - Implement and test LUT3

Pull Request - State: closed - Opened by satnam6502 over 4 years ago - 1 comment

#96 - Create tests and LUT1 INV and LUT2 AND

Pull Request - State: closed - Opened by satnam6502 over 4 years ago

#96 - Create tests and LUT1 INV and LUT2 AND

Pull Request - State: closed - Opened by satnam6502 over 4 years ago

#95 - Also generate post-synthesis Verilog

Pull Request - State: closed - Opened by satnam6502 over 4 years ago

#95 - Also generate post-synthesis Verilog

Pull Request - State: closed - Opened by satnam6502 over 4 years ago

#94 - Investigate kappa phoas conversion without explicit environment

Issue - State: closed - Opened by blaxill over 4 years ago - 2 comments
Labels: P4

#94 - Investigate kappa phoas conversion without explicit environment

Issue - State: closed - Opened by blaxill over 4 years ago - 2 comments
Labels: P4

#93 - Improve kappa syntax

Pull Request - State: closed - Opened by blaxill over 4 years ago - 2 comments

#93 - Improve kappa syntax

Pull Request - State: closed - Opened by blaxill over 4 years ago - 2 comments

#92 - Emit kappa variable lookup arrow directly

Pull Request - State: closed - Opened by blaxill over 4 years ago - 1 comment

#92 - Emit kappa variable lookup arrow directly

Pull Request - State: closed - Opened by blaxill over 4 years ago - 1 comment

#91 - Support LUT1 and LUT2

Pull Request - State: closed - Opened by satnam6502 over 4 years ago - 1 comment

#91 - Support LUT1 and LUT2

Pull Request - State: closed - Opened by satnam6502 over 4 years ago - 1 comment

#90 - Support LUT1 and LUT2

Pull Request - State: closed - Opened by satnam6502 over 4 years ago

#90 - Support LUT1 and LUT2

Pull Request - State: closed - Opened by satnam6502 over 4 years ago

#89 - EDIF to Cava translation

Pull Request - State: closed - Opened by satnam6502 over 4 years ago

#89 - EDIF to Cava translation

Pull Request - State: closed - Opened by satnam6502 over 4 years ago

#88 - Remove dependency on iverilog

Pull Request - State: closed - Opened by satnam6502 over 4 years ago

#88 - Remove dependency on iverilog

Pull Request - State: closed - Opened by satnam6502 over 4 years ago

#87 - Switch arrow tests to produce Verilator testbenches

Pull Request - State: closed - Opened by satnam6502 over 4 years ago - 1 comment

#87 - Switch arrow tests to produce Verilator testbenches

Pull Request - State: closed - Opened by satnam6502 over 4 years ago - 1 comment

#86 - Convert compute in Xilinx adder tree example to Example as regression test

Pull Request - State: closed - Opened by satnam6502 over 4 years ago - 2 comments

#86 - Convert compute in Xilinx adder tree example to Example as regression test

Pull Request - State: closed - Opened by satnam6502 over 4 years ago - 2 comments

#85 - Add a _CoqProject to use for vscoq for Visual Studio Code

Pull Request - State: closed - Opened by satnam6502 over 4 years ago - 1 comment

#85 - Add a _CoqProject to use for vscoq for Visual Studio Code

Pull Request - State: closed - Opened by satnam6502 over 4 years ago - 1 comment

#84 - Proofs relating the col combinator to the below combinator

Pull Request - State: closed - Opened by satnam6502 over 4 years ago - 1 comment

#84 - Proofs relating the col combinator to the below combinator

Pull Request - State: closed - Opened by satnam6502 over 4 years ago - 1 comment

#83 - Syntax and compilation to arrows

Pull Request - State: closed - Opened by blaxill over 4 years ago - 1 comment

#83 - Syntax and compilation to arrows

Pull Request - State: closed - Opened by blaxill over 4 years ago - 1 comment

#82 - Add support for wiring up debug ports for logic analyzer.

Pull Request - State: closed - Opened by satnam6502 over 4 years ago - 1 comment

#82 - Add support for wiring up debug ports for logic analyzer.

Pull Request - State: closed - Opened by satnam6502 over 4 years ago - 1 comment

#81 - Avoid logic pruning in Xilinx FPGA tools for adder-trees

Pull Request - State: closed - Opened by satnam6502 over 4 years ago

#81 - Avoid logic pruning in Xilinx FPGA tools for adder-trees

Pull Request - State: closed - Opened by satnam6502 over 4 years ago

#80 - Update Arrow/Instances/Netlist.v for the new netlist types

Pull Request - State: closed - Opened by blaxill over 4 years ago

#80 - Update Arrow/Instances/Netlist.v for the new netlist types

Pull Request - State: closed - Opened by blaxill over 4 years ago

#78 - Add support for multi-dimensional input bit-vectors

Pull Request - State: closed - Opened by satnam6502 over 4 years ago

#78 - Add support for multi-dimensional input bit-vectors

Pull Request - State: closed - Opened by satnam6502 over 4 years ago

#76 - Automatically generate Verilator SystemVerilog test benches from Coq

Issue - State: closed - Opened by satnam6502 over 4 years ago - 1 comment

#76 - Automatically generate Verilator SystemVerilog test benches from Coq

Issue - State: closed - Opened by satnam6502 over 4 years ago - 1 comment

#75 - Automatically generate testbenchs for circuits and test witg Verilator

Pull Request - State: closed - Opened by satnam6502 over 4 years ago - 2 comments

#75 - Automatically generate testbenchs for circuits and test witg Verilator

Pull Request - State: closed - Opened by satnam6502 over 4 years ago - 2 comments

#74 - Fix the representation of port declarations

Pull Request - State: closed - Opened by satnam6502 over 4 years ago

#74 - Fix the representation of port declarations

Pull Request - State: closed - Opened by satnam6502 over 4 years ago

#73 - By default do not clean for make

Pull Request - State: closed - Opened by satnam6502 over 4 years ago

#73 - By default do not clean for make

Pull Request - State: closed - Opened by satnam6502 over 4 years ago

#72 - Cleanup

Pull Request - State: closed - Opened by satnam6502 over 4 years ago

#72 - Cleanup

Pull Request - State: closed - Opened by satnam6502 over 4 years ago

#71 - Use balanced tuple for adder tree input

Pull Request - State: closed - Opened by satnam6502 over 4 years ago

#71 - Use balanced tuple for adder tree input

Pull Request - State: closed - Opened by satnam6502 over 4 years ago

#70 - Add circuit interface mechansim

Pull Request - State: closed - Opened by satnam6502 over 4 years ago - 1 comment

#70 - Add circuit interface mechansim

Pull Request - State: closed - Opened by satnam6502 over 4 years ago - 1 comment

#69 - Make adder semantics assume bit-growth implicitly

Pull Request - State: closed - Opened by satnam6502 over 4 years ago - 1 comment

#69 - Make adder semantics assume bit-growth implicitly

Pull Request - State: closed - Opened by satnam6502 over 4 years ago - 1 comment

#68 - Switch from nat to N for values convertible to bit-vectors

Pull Request - State: closed - Opened by satnam6502 over 4 years ago - 1 comment

#68 - Switch from nat to N for values convertible to bit-vectors

Pull Request - State: closed - Opened by satnam6502 over 4 years ago - 1 comment

#67 - Enable Arrows with the updated Netlist

Pull Request - State: closed - Opened by blaxill over 4 years ago

#67 - Enable Arrows with the updated Netlist

Pull Request - State: closed - Opened by blaxill over 4 years ago

#66 - Add Arrow notation

Pull Request - State: closed - Opened by blaxill over 4 years ago

#66 - Add Arrow notation

Pull Request - State: closed - Opened by blaxill over 4 years ago

#65 - Stratify the type type and de-Vectorize

Pull Request - State: closed - Opened by satnam6502 over 4 years ago

#65 - Stratify the type type and de-Vectorize

Pull Request - State: closed - Opened by satnam6502 over 4 years ago

#64 - Move arrow test-benches to correct location and activate

Pull Request - State: closed - Opened by satnam6502 over 4 years ago

#64 - Move arrow test-benches to correct location and activate

Pull Request - State: closed - Opened by satnam6502 over 4 years ago

#63 - Move arrow versions of xor and loopedNAND to correct directory and ac…

Pull Request - State: closed - Opened by satnam6502 over 4 years ago - 1 comment

#62 - Add gcc to nix build

Pull Request - State: closed - Opened by satnam6502 over 4 years ago

#61 - Convert adder_tree8_4 test bench to use verilator.

Pull Request - State: closed - Opened by satnam6502 over 4 years ago

#60 - Fix .gitignore for arrow examples

Pull Request - State: closed - Opened by satnam6502 over 4 years ago

#59 - SystemVerilog test bench for adder_tree4_8

Pull Request - State: closed - Opened by satnam6502 over 4 years ago - 1 comment

#58 - Remove duplicate combinator definitions

Pull Request - State: closed - Opened by satnam6502 over 4 years ago

#57 - Change unsignedAdder to take explicit sum length

Pull Request - State: closed - Opened by satnam6502 over 4 years ago - 1 comment

#55 - Reintroduce shape from v2 and separate primitives from binding sites

Pull Request - State: closed - Opened by blaxill over 4 years ago - 1 comment

#54 - Proofs about nat to bitvector conversion

Pull Request - State: closed - Opened by satnam6502 over 4 years ago - 2 comments

#53 - Prove properties about nat to bit-vector conversion

Issue - State: closed - Opened by satnam6502 over 4 years ago - 1 comment

#52 - Use library Coq.NArith.Ndigits for nat to bitvector conversion.

Pull Request - State: closed - Opened by satnam6502 over 4 years ago

#50 - Investigate selective Coq to Haskell extraction

Issue - State: closed - Opened by blaxill over 4 years ago - 2 comments
Labels: P3

#49 - Pin versions

Pull Request - State: closed - Opened by blaxill over 4 years ago - 1 comment

#48 - Move examples out of Monad and Arrow directories

Pull Request - State: closed - Opened by satnam6502 over 4 years ago - 3 comments

#47 - Move Cava files actually under the Cava directory

Pull Request - State: closed - Opened by satnam6502 over 4 years ago

#46 - Update documentation to reflect new directory structure

Pull Request - State: closed - Opened by satnam6502 over 4 years ago

#45 - Move cava into a subdirectory and make cava-examples a peer

Pull Request - State: closed - Opened by satnam6502 over 4 years ago - 1 comment

#44 - Add syntax for building Arrows

Issue - State: closed - Opened by blaxill over 4 years ago

#43 - Rename the monadic Cava code into a Monad directory

Pull Request - State: closed - Opened by satnam6502 over 4 years ago

#42 - Rename files to support use of monad and arrow variants of Cava

Issue - State: closed - Opened by satnam6502 over 4 years ago - 1 comment
Labels: enhancement

#41 - Improve directory structure for Cava

Issue - State: closed - Opened by satnam6502 over 4 years ago - 6 comments
Labels: question

#40 - Banish non-decreasing index vectors (downto style)

Issue - State: closed - Opened by satnam6502 over 4 years ago - 2 comments
Labels: enhancement

#39 - A first attempt at an adder-tree

Pull Request - State: closed - Opened by satnam6502 over 4 years ago - 5 comments

#38 - Produce an recursive adder tree example

Issue - State: closed - Opened by satnam6502 over 4 years ago - 1 comment