Ecosyste.ms: Issues

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GitHub / progranism/Open-Source-FPGA-Bitcoin-Miner issues and pull requests

#39 - [email protected]

Issue - State: closed - Opened by Chanceiam321 over 2 years ago

#36 - Compare simulation with golden hash values

Issue - State: open - Opened by aywkwok over 2 years ago

#34 - Image for Intel CV SoC

Issue - State: open - Opened by Sectorchan over 3 years ago

#33 - cyclone 10 kit support

Issue - State: open - Opened by sbelodon over 3 years ago

#32 - Help: Intel Cyclone 10 LP

Issue - State: open - Opened by GuntasSinghProg5 almost 4 years ago

#31 - Am I really mining?

Issue - State: open - Opened by arbonino over 4 years ago - 15 comments

#30 - Is there possibilitiy to run this on our lattice board?

Issue - State: open - Opened by goran-mahovlic over 5 years ago - 2 comments

#29 - intel Quartus ii compiler

Issue - State: closed - Opened by ghost about 6 years ago

#28 - IDX is not defined(sha256_transform)

Issue - State: closed - Opened by ghost about 6 years ago - 5 comments

#27 - Help editing for a papilio duo

Issue - State: open - Opened by cdeluca3 about 6 years ago

#26 - Unable to communicate with FPGA firmware on new device port

Issue - State: closed - Opened by penguin359 about 6 years ago - 14 comments

#25 - help

Issue - State: open - Opened by dkmengjin over 6 years ago

#24 - Localization/Translation

Issue - State: open - Opened by agentzero1 over 6 years ago

#23 - Issue with program-fpga-board.bat

Issue - State: open - Opened by yxp99 almost 7 years ago - 5 comments

#22 - Need help on where to start

Issue - State: closed - Opened by tleydxdy over 7 years ago

#21 - Hash rate is 0.02 MH/s

Issue - State: open - Opened by ngcaotri almost 8 years ago - 2 comments

#20 - No "stratum+tcp" support?

Issue - State: open - Opened by ahogen over 8 years ago - 4 comments

#19 - Missing Verilog component: altsource_probe_component

Issue - State: closed - Opened by Rasoul77 over 10 years ago - 1 comment

#18 - FPGA selection added to mine script

Pull Request - State: closed - Opened by chrishaw about 11 years ago - 2 comments

#17 - needs a plug in for bfgminer

Issue - State: open - Opened by Hardcore-fs over 11 years ago - 10 comments

#15 - KC705

Issue - State: open - Opened by Hardcore-fs over 11 years ago - 2 comments

#14 - Missing verilog files

Issue - State: closed - Opened by vikasg29 over 11 years ago - 1 comment

#13 - Missing verilog files

Issue - State: closed - Opened by vikasg29 over 11 years ago - 1 comment

#12 - miner.py : Timed out waiting for FPGA to accept work

Issue - State: closed - Opened by roman3017 over 11 years ago

#11 - small device for testing.

Issue - State: open - Opened by tintinz over 11 years ago - 2 comments

#10 - Running on FLEX devices

Issue - State: open - Opened by Rasta8889 over 12 years ago - 2 comments

#9 - 100% Rejection

Issue - State: open - Opened by nonverba over 12 years ago - 2 comments

#8 - Improve code for K lookup to increase achievable clock speed.

Pull Request - State: closed - Opened by makomk about 13 years ago - 4 comments

#7 - Miner.bat for other (smaller) devices

Issue - State: open - Opened by ghost over 13 years ago - 1 comment

#6 - Stratix IV VHDL project

Pull Request - State: closed - Opened by IAmNotDorian over 13 years ago - 1 comment

#5 - Xilinx VHDL synthesizing forever

Issue - State: closed - Opened by masta79 over 13 years ago - 3 comments

#4 - Please add missing Verilog files

Issue - State: open - Opened by Ringel over 13 years ago - 4 comments

#3 - Sorry, still learning git

Pull Request - State: closed - Opened by udif over 13 years ago - 1 comment

#2 - reduce block size/throughput by a factor of 2^N

Pull Request - State: closed - Opened by udif over 13 years ago

#1 - Clarified Requirements

Pull Request - State: closed - Opened by interfect over 13 years ago - 1 comment