Ecosyste.ms: Issues
An open API service for providing issue and pull request metadata for open source projects.
GitHub / princetonuniversity/prga issues and pull requests
#29 - Synthesis
Issue -
State: open - Opened by minsikky 4 months ago
- 1 comment
#28 - Power estimation
Issue -
State: open - Opened by OlinLai about 1 year ago
- 1 comment
#27 - failed to find matching architecture model for '$_DFF_PP0'
Issue -
State: closed - Opened by WhiteStart over 1 year ago
- 3 comments
#26 - When compiling under msys2, I encountered the following error
Issue -
State: closed - Opened by dingzex almost 3 years ago
- 5 comments
#25 - Install Error
Issue -
State: closed - Opened by dingzex over 3 years ago
- 7 comments
#24 - Build error on Ubuntu 20.04
Issue -
State: closed - Opened by mjc0608 over 3 years ago
- 3 comments
#23 - Support ROM mode for block RAMs
Issue -
State: closed - Opened by angl-dev almost 4 years ago
- 1 comment
Labels: enhancement
#22 - Use generic FASM and config-specific bitgen tool
Issue -
State: closed - Opened by angl-dev almost 4 years ago
- 1 comment
Labels: enhancement
#21 - Make context creation independent to configuration circuitry type
Issue -
State: closed - Opened by angl-dev almost 4 years ago
- 1 comment
Labels: enhancement
#20 - [CI] Initialize CI
Pull Request -
State: closed - Opened by angl-dev about 4 years ago
#19 - Add [configurable, programmable] DSP block
Issue -
State: open - Opened by angl-dev about 4 years ago
- 1 comment
#18 - Demote prga.py from submodule to a regular directory
Issue -
State: open - Opened by angl-dev about 4 years ago
#17 - More testcases
Issue -
State: open - Opened by angl-dev about 4 years ago
#16 - Easier Bitstream Debug
Issue -
State: closed - Opened by angl-dev about 4 years ago
- 1 comment
#15 - Review module designs
Issue -
State: closed - Opened by angl-dev over 4 years ago
- 1 comment
#14 - Add an option to generate SystemVerilog files
Issue -
State: closed - Opened by angl-dev over 4 years ago
#13 - Getting an error during implemantation and simulating of tiny_k4_N2_8x8
Issue -
State: closed - Opened by naeimiali7 over 4 years ago
- 2 comments
#12 - new changes
Pull Request -
State: closed - Opened by buddynohair over 4 years ago
- 9 comments
#11 - new blocks and bitstream
Issue -
State: closed - Opened by buddynohair over 4 years ago
- 2 comments
#10 - add new module
Issue -
State: closed - Opened by buddynohair over 4 years ago
- 33 comments
#9 - Cocotb Integration for Automated Testing
Pull Request -
State: closed - Opened by crusader2000 over 4 years ago
#8 - bitstream generation
Issue -
State: closed - Opened by buddynohair over 4 years ago
- 2 comments
#7 - Error while building fpga_tiny_k4_N2_8x8
Issue -
State: closed - Opened by kiranhollag over 4 years ago
- 11 comments
#6 - Updating delay model
Issue -
State: open - Opened by tanvir-a almost 5 years ago
- 2 comments
Labels: enhancement
#5 - Error while generating a small FPGA
Issue -
State: closed - Opened by tanvir-a about 5 years ago
- 1 comment
#4 - Add link from https://prga.rtfd.io to GitHub repository
Issue -
State: closed - Opened by mithro over 5 years ago
- 5 comments
#3 - Support Python 3!
Issue -
State: closed - Opened by mithro about 6 years ago
- 1 comment
#2 - Add a link to https://prga.rtfd.io into README file
Issue -
State: closed - Opened by mithro about 6 years ago
- 1 comment
#1 - Add a LICENSE or COPYING file
Issue -
State: closed - Opened by mithro about 6 years ago
- 3 comments