Ecosyste.ms: Issues
An open API service for providing issue and pull request metadata for open source projects.
GitHub / openxiangshan/utility issues and pull requests
#85 - feat(dbltrp): add critical-error help
Pull Request -
State: closed - Opened by lewislzh 26 days ago
#84 - feat(SRAM): use `ValName` for better and steady naming
Pull Request -
State: open - Opened by Tang-Haojin 26 days ago
#83 - feat(SRAMTemplate): Add param `withClockGate` at SRAMTemplate
Pull Request -
State: closed - Opened by Lawrence-ID about 1 month ago
#82 - fix(hold): add DataHoldBypassInit
Pull Request -
State: closed - Opened by sinceforYy 2 months ago
#81 - feat(HPM): add basic HPMs
Pull Request -
State: closed - Opened by yu-yake2002 2 months ago
#80 - feat(indexableCAM): Tage BT table needs to use index to access CAMTem…
Pull Request -
State: closed - Opened by sleep-zzz 2 months ago
#79 - feat(IntBuffer): add cdc option for synchronizer
Pull Request -
State: closed - Opened by Tang-Haojin 2 months ago
#78 - DataModuleTemplate: remove Negedge prefix of module name
Pull Request -
State: closed - Opened by xiaofeibao-xjtu 3 months ago
#77 - AXI4Utils: add AXI4Error to handle system level illegal address access
Pull Request -
State: closed - Opened by linjuanZ 3 months ago
#76 - [MBIST] Add mbist infrastructure (#71)
Pull Request -
State: open - Opened by good-circle 4 months ago
#75 - IntBuffer: add depth parameter
Pull Request -
State: closed - Opened by Tang-Haojin 4 months ago
#74 - ChiselDB: fix char* buffer may overflow
Pull Request -
State: closed - Opened by Ivyfeather 4 months ago
#73 - clock gate: add functions for duplicate regs
Pull Request -
State: closed - Opened by Lawrence-ID 4 months ago
#72 - XSLogPerf: transfer XSLogPerf from XiangShan repository
Pull Request -
State: closed - Opened by Tang-Haojin 5 months ago
#71 - [MBIST] Add mbist infrastructure
Pull Request -
State: closed - Opened by Siudya 5 months ago
#70 - ClockGate: use `VERILATOR_LEGACY` for verilator version less than 5
Pull Request -
State: closed - Opened by Tang-Haojin 5 months ago
#69 - clockgate: set wireInit to avoid X in vcs simulation
Pull Request -
State: closed - Opened by Maxpicca-Li 5 months ago
#68 - QPtrMatchMatrix: add flag as match condition
Pull Request -
State: closed - Opened by xiaofeibao-xjtu 6 months ago
#67 - clockgate: set default initialization with 0
Pull Request -
State: closed - Opened by Maxpicca-Li 6 months ago
#66 - util: add class segmented addr
Pull Request -
State: closed - Opened by eastonman 6 months ago
- 1 comment
#65 - typo: change hardware to Chisel type in clockgate files
Pull Request -
State: closed - Opened by Maxpicca-Li 6 months ago
- 1 comment
#64 - clockgate: add more methods and fix original bug
Pull Request -
State: closed - Opened by Maxpicca-Li 6 months ago
- 6 comments
#63 - util: remove cloneType in ParallelMux
Pull Request -
State: closed - Opened by eastonman 7 months ago
- 1 comment
#62 - Constantin: use BigInt initValue for createRecord
Pull Request -
State: closed - Opened by poemonsense 7 months ago
#61 - buskey: add PBOP
Pull Request -
State: closed - Opened by Maxpicca-Li 7 months ago
#60 - Clock: Encapsulate ClockGate as an object
Pull Request -
State: closed - Opened by xiaokamikami 7 months ago
#59 - module: add clock_gate wire
Pull Request -
State: closed - Opened by xiaokamikami 7 months ago
#58 - Constantin: use compile-time env if possible
Pull Request -
State: closed - Opened by poemonsense 8 months ago
#57 - util: add hasInit to DelayNWithValid
Pull Request -
State: closed - Opened by eastonman 9 months ago
#56 - util: pick clock gating util from nanhu
Pull Request -
State: closed - Opened by eastonman 9 months ago
- 1 comment
#55 - Utility: improve clock-gating coverage
Pull Request -
State: closed - Opened by sumailyyc 9 months ago
#54 - chiseldb: fix typo
Pull Request -
State: open - Opened by wakafa1 10 months ago
#53 - Fix switch chisel db
Pull Request -
State: closed - Opened by Maxpicca-Li 10 months ago
#53 - Fix switch chisel db
Pull Request -
State: closed - Opened by Maxpicca-Li 10 months ago
#52 - UIntUtils: add UIntCompressor & UIntExtractor
Pull Request -
State: closed - Opened by sinsanction 10 months ago
#51 - chore: replace deprecated APIs
Pull Request -
State: closed - Opened by Tang-Haojin 11 months ago
#50 - Support bitmasking in SRAMTemplate
Pull Request -
State: closed - Opened by eastonman 11 months ago
- 1 comment
#49 - Constantin: avoid assigning DPI-C value to wire directly
Pull Request -
State: closed - Opened by Tang-Haojin 11 months ago
#48 - CircularQueuePtr: add function to calculate empty entries
Pull Request -
State: closed - Opened by huxuan0307 11 months ago
#47 - ChiselDB: init parameter string in verilog for palladium
Pull Request -
State: closed - Opened by cailuoshan 12 months ago
#46 - ConstantIn: support multi calling from different instances
Pull Request -
State: closed - Opened by Tang-Haojin about 1 year ago
#45 - ChiselDB: dynamically append hartid for table name and site name
Pull Request -
State: open - Opened by Tang-Haojin about 1 year ago
- 1 comment
#44 - constantin: fix missing header
Pull Request -
State: closed - Opened by wakafa1 about 1 year ago
#43 - fix: constantin init when load from stdin
Pull Request -
State: closed - Opened by cebarobot about 1 year ago
#42 - fix: pass bypassWrite through
Pull Request -
State: closed - Opened by eastonman about 1 year ago
- 1 comment
#41 - util: implement ValidIOBoradcast initially
Pull Request -
State: closed - Opened by wakafa1 about 1 year ago
#40 - chore: bump Chisel 3.6.0 and Scala 2.13
Pull Request -
State: closed - Opened by poemonsense about 1 year ago
#39 - Bump Chisel and rocket-chip
Pull Request -
State: closed - Opened by poemonsense about 1 year ago
#38 - Disable Verilator tracing for LogPerfHelper blackbox
Pull Request -
State: closed - Opened by poemonsense about 1 year ago
#37 - chore: remove deprecated brackets, APIs, etc.
Pull Request -
State: closed - Opened by Tang-Haojin about 1 year ago
#36 - BoringUtils: remove exciting utils
Pull Request -
State: closed - Opened by Tang-Haojin about 1 year ago
#35 - log: use XMR instead of boring utils for logging
Pull Request -
State: closed - Opened by Tang-Haojin about 1 year ago
#34 - Revert "perf: use DPI-C instead of boring utils for perf counters"
Pull Request -
State: closed - Opened by Tang-Haojin about 1 year ago
#33 - ChiselDB: add `const` to avoid compiler warnings
Pull Request -
State: closed - Opened by poemonsense about 1 year ago
#32 - perf: use DPI-C instead of boring utils for perf counters
Pull Request -
State: closed - Opened by Tang-Haojin about 1 year ago
#31 - ResetGen: add CellNode
Pull Request -
State: closed - Opened by Ivyfeather about 1 year ago
#30 - bus: add more sources
Pull Request -
State: closed - Opened by happy-lx about 1 year ago
#29 - reqsource: enrich prefetch reqsources
Pull Request -
State: closed - Opened by wakafa1 over 1 year ago
#28 - TLUtils: change `MemReqSource_internal` into `MemReqSource`
Pull Request -
State: closed - Opened by Tang-Haojin over 1 year ago
#27 - chiseldb: add select-db to select database wanted to dump
Pull Request -
State: closed - Opened by Lemover over 1 year ago
#26 - OneHot: add functional def `OHToUIntStartOne`
Pull Request -
State: closed - Opened by Maxpicca-Li over 1 year ago
#25 - Fix version: merge `XiangShan/master/utility` into `utility/main`
Pull Request -
State: closed - Opened by Maxpicca-Li over 1 year ago
Labels: invalid
#24 - Fix version: merge `XiangShan/master/utility` into `utility/main`
Pull Request -
State: closed - Opened by Maxpicca-Li over 1 year ago
Labels: invalid
#23 - ChiselDB: fix createTable with the same name and hw type
Pull Request -
State: closed - Opened by poemonsense over 1 year ago
#22 - Change chiseldb argument and move tllog in
Pull Request -
State: closed - Opened by wakafa1 over 1 year ago
#21 - constant: fix assert
Pull Request -
State: closed - Opened by Maxpicca-Li over 1 year ago
#20 - top-down: support elaborated top down
Pull Request -
State: closed - Opened by Tang-Haojin over 1 year ago
#19 - Fix util constant
Pull Request -
State: closed - Opened by Maxpicca-Li over 1 year ago
#18 - add RegisterSlice.scala
Pull Request -
State: closed - Opened by Guo-HY over 1 year ago
- 1 comment
#17 - ParallelMux: add new APIs
Pull Request -
State: closed - Opened by Tang-Haojin over 1 year ago
#16 - chisledb: add envFPGA situation
Pull Request -
State: closed - Opened by Maxpicca-Li over 1 year ago
#15 - Tool: cancel DIP-C write when in FPGA
Pull Request -
State: closed - Opened by Maxpicca-Li over 1 year ago
#14 - code opt: add write function in FileRegisters
Pull Request -
State: closed - Opened by Maxpicca-Li over 1 year ago
#13 - CirculatQueuePtr: add more useful APIs
Pull Request -
State: closed - Opened by Tang-Haojin over 1 year ago
#12 - constantin: fix bug which reduced emputy map
Pull Request -
State: closed - Opened by Maxpicca-Li over 1 year ago
#11 - constantin: correct the code logic and add assert
Pull Request -
State: closed - Opened by Maxpicca-Li over 1 year ago
#10 - BitUtils: add SelectFirstN
Pull Request -
State: closed - Opened by cz4e almost 2 years ago
#9 - BitUtils: add SelectFirstN
Pull Request -
State: closed - Opened by cz4e almost 2 years ago
#8 - BitUtils: add SelectFirstN
Pull Request -
State: closed - Opened by cz4e almost 2 years ago
#7 - Add constant solver support
Pull Request -
State: closed - Opened by happy-lx almost 2 years ago
#6 - Add Constantin
Pull Request -
State: closed - Opened by chenguokai almost 2 years ago
#5 - misc: add RRArbiterInit
Pull Request -
State: closed - Opened by AugustusWillisWang almost 2 years ago
#4 - Master use async reset
Pull Request -
State: closed - Opened by wakafa1 almost 2 years ago
#3 - LFSR64: support assign seed or use rand seed
Pull Request -
State: closed - Opened by AugustusWillisWang almost 2 years ago
#2 - misc: rename directory
Pull Request -
State: closed - Opened by wakafa1 almost 2 years ago
#1 - Decouple Utility from projects
Pull Request -
State: closed - Opened by wakafa1 almost 2 years ago
- 2 comments