Ecosyste.ms: Issues

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GitHub / openhwgroup/cva5 issues and pull requests

#27 - Preliminary OS support

Pull Request - State: open - Opened by CKeilbar 3 months ago

#26 - Add FPU (squashed)

Pull Request - State: closed - Opened by CKeilbar 9 months ago - 3 comments

#24 - Clarification Regarding Simulation of CVA-5 Processor

Issue - State: open - Opened by Tanishqgithub 10 months ago - 1 comment

#23 - Add FPU

Pull Request - State: closed - Opened by CKeilbar 12 months ago - 14 comments

#22 - Peripheral Reads do not wait for retiring, can cause state corruption

Issue - State: closed - Opened by ramonwirsch about 1 year ago - 1 comment

#21 - State of AMO support

Issue - State: open - Opened by ramonwirsch about 1 year ago - 2 comments

#18 - Hardware Setup

Issue - State: open - Opened by leloc0609 about 1 year ago

#17 - how to use jtag in AMD FGPA

Issue - State: open - Opened by mola1222 over 1 year ago

#16 - Fix invalidation address and non power of 2 fifos

Pull Request - State: closed - Opened by CKeilbar over 1 year ago - 3 comments

#15 - AXI DDR

Issue - State: closed - Opened by maheshejs over 1 year ago - 1 comment

#14 - cva5 simulation using questasim

Issue - State: open - Opened by AhmedMostafa98 over 1 year ago - 6 comments

#13 - Code cleanups

Pull Request - State: closed - Opened by e-matthews over 1 year ago

#12 - Improvements for competition setup

Pull Request - State: closed - Opened by e-matthews over 1 year ago

#11 - Cache architecture of the previous version (Taiga)

Issue - State: open - Opened by demyana123 over 1 year ago - 3 comments
Labels: question

#10 - Cache architecture of the CVA5 processor?

Issue - State: open - Opened by Mohamed1984 almost 2 years ago - 3 comments
Labels: question

#10 - Cache architecture of the CVA5 processor?

Issue - State: open - Opened by Mohamed1984 almost 2 years ago - 3 comments
Labels: question

#9 - Fixes potential load/store ordering issue when store queue is full

Pull Request - State: closed - Opened by e-matthews almost 2 years ago

#8 - CVA5 university competition branch

Pull Request - State: closed - Opened by e-matthews almost 2 years ago

#7 - L2: Move be (i.e. wstrb for AXI) into the data FIFO (Fixes #6)

Pull Request - State: closed - Opened by flmeisel about 2 years ago - 2 comments

#5 - Minor fixes

Pull Request - State: closed - Opened by e-matthews over 2 years ago

#4 - Fetch and Load-Store Interface Refactor and LiteX Support

Pull Request - State: closed - Opened by e-matthews over 2 years ago

#3 - Taiga to CVA5 renaming

Pull Request - State: closed - Opened by e-matthews over 2 years ago

#2 - Physical address space, starting at 0x00 in M Mode, fail at first control flow

Issue - State: closed - Opened by c-93 over 2 years ago - 2 comments

#1 - Post-transfer Updates

Pull Request - State: closed - Opened by e-matthews almost 3 years ago