Ecosyste.ms: Issues

An open API service for providing issue and pull request metadata for open source projects.

GitHub / openhwgroup/corev-gcc issues and pull requests

#111 - XCVbitmanip: merge custom and standard builtins

Issue - State: open - Opened by MaryBennett 4 months ago

#110 - XCVsimd builtin optimisation enhancement

Pull Request - State: open - Opened by zhixiao-zhang 5 months ago

#109 - Modify xcvmem test cases to run for Os, Oz and Og

Pull Request - State: closed - Opened by zhixiao-zhang 7 months ago - 1 comment

#108 - Post-inc: tests don't generate instructions for Og

Issue - State: open - Opened by MaryBennett 8 months ago - 1 comment
Labels: enhancement

#107 - Update CORE-V documentation.

Pull Request - State: closed - Opened by jeremybennett 8 months ago - 1 comment

#106 - CORE-V bitmanip builtin failure with bclr/bset

Issue - State: closed - Opened by jeremybennett 9 months ago - 2 comments
Labels: bug

#105 - CORE-V bitmanip extract failures with -O1

Issue - State: closed - Opened by jeremybennett 9 months ago - 1 comment
Labels: bug

#103 - Roll forward - 19th March 2024

Pull Request - State: closed - Opened by Slattz 11 months ago - 1 comment

#102 - Rebase on non-broken upstream (building with newlib)

Pull Request - State: closed - Opened by simonpcook 11 months ago

#101 - HW Loop produces an ICE during building

Issue - State: closed - Opened by Slattz 12 months ago - 2 comments

#100 - Add header file for XCVsimd

Pull Request - State: closed - Opened by MaryBennett about 1 year ago - 1 comment

#99 - Add header file for XCVbitmanip

Pull Request - State: closed - Opened by MaryBennett about 1 year ago - 1 comment

#98 - Add header file for XCVmac

Pull Request - State: closed - Opened by MaryBennett about 1 year ago - 1 comment

#97 - Add header file for XCVelw

Pull Request - State: closed - Opened by MaryBennett about 1 year ago - 1 comment

#96 - Change xcvmem tests to run for Os and Oz

Pull Request - State: closed - Opened by MaryBennett about 1 year ago - 1 comment

#95 - Roll forward

Pull Request - State: closed - Opened by MaryBennett about 1 year ago

#94 - Add header file for XCValu

Pull Request - State: closed - Opened by MaryBennett about 1 year ago - 1 comment

#93 - Change the priority of the XCVmem instructions

Pull Request - State: closed - Opened by MaryBennett about 1 year ago - 1 comment

#92 - pseudo instruction "LA" not translating to correct instructions

Issue - State: closed - Opened by dd-vaibhavjain about 1 year ago - 5 comments
Labels: bug

#91 - Tests added for XCVhwlp

Pull Request - State: closed - Opened by MaryBennett about 1 year ago - 1 comment

#89 - Add regression tests for hardware loop failures in issues #83 and #84

Issue - State: closed - Opened by MaryBennett about 1 year ago - 1 comment

#88 - xcvmem `mem (reg + reg)` instructions require corev.md to be above movSI.

Issue - State: closed - Opened by MaryBennett about 1 year ago - 1 comment
Labels: enhancement

#88 - xcvmem `mem (reg + reg)` instructions require corev.md to be above movSI.

Issue - State: closed - Opened by MaryBennett about 1 year ago - 1 comment
Labels: enhancement

#87 - Roll forward

Pull Request - State: closed - Opened by MaryBennett about 1 year ago

#86 - .option norvc is ignored with Zca

Issue - State: closed - Opened by Wren6991 about 1 year ago - 2 comments

#85 - Update README

Pull Request - State: closed - Opened by MaryBennett about 1 year ago - 3 comments

#84 - Hardware loops causes ICE in final_scan_insn_1

Issue - State: closed - Opened by jeremybennett over 1 year ago - 5 comments
Labels: bug

#83 - Hardware loops causes relocation truncated to fit: R_RISCV_CVPCREL_UI12

Issue - State: closed - Opened by jeremybennett over 1 year ago - 3 comments
Labels: bug

#82 - Exclude CORE-V memory tests for compressed code generation.

Pull Request - State: closed - Opened by jeremybennett over 1 year ago - 1 comment

#81 - Fix for Issue #77

Pull Request - State: closed - Opened by MaryBennett over 1 year ago - 1 comment

#80 - Jwr gcc14 xcvhwlp

Pull Request - State: closed - Opened by MaryBennett over 1 year ago

#79 - backport CORE-V HW loop.

Pull Request - State: closed - Opened by MaryBennett over 1 year ago

#78 - Hardware Loops march option not recognized

Issue - State: closed - Opened by pascalgouedo over 1 year ago - 1 comment

#77 - Incorrect code generation with PULP march with 20231017 release

Issue - State: closed - Opened by pascalgouedo over 1 year ago - 1 comment
Labels: bug

#76 - Jwr gcc14 xcvhwlp

Pull Request - State: closed - Opened by MaryBennett over 1 year ago

#75 - Fix mem_plus_reg predicate

Pull Request - State: closed - Opened by MaryBennett over 1 year ago - 2 comments

#74 - [XCVmem] Normal register-immediate store not recognized

Issue - State: closed - Opened by MaryBennett over 1 year ago - 3 comments
Labels: bug

#72 - Fix cv.shuffle.b.sci immediate operand

Pull Request - State: closed - Opened by MaryBennett over 1 year ago - 2 comments

#71 - Fixes to xcvbitmanip and xcvsimd

Pull Request - State: closed - Opened by MaryBennett over 1 year ago - 4 comments

#70 - unrecognized opcode 'csrr' extension 'zicsr' required

Issue - State: closed - Opened by promodkumar-ashling over 1 year ago - 6 comments
Labels: help wanted

#69 - WIP: Added a CORE-V builtins header file

Pull Request - State: closed - Opened by MaryBennett over 1 year ago - 1 comment

#68 - cv-simd-shufflei* incorrect builtin

Issue - State: closed - Opened by MaryBennett over 1 year ago - 2 comments
Labels: bug

#67 - How to check COREV_CLUSTER for Event Load Instruction

Issue - State: closed - Opened by ChunyuLiao over 1 year ago - 2 comments

#66 - Prevent non-xcvmem post-inc load/stores

Pull Request - State: closed - Opened by MaryBennett over 1 year ago - 2 comments

#65 - Added __builtin_riscv_cv_simd_neg_[h,b]

Pull Request - State: closed - Opened by MaryBennett over 1 year ago - 2 comments

#64 - illegal operand error for "sw" operation

Issue - State: closed - Opened by superflyers over 1 year ago - 2 comments

#63 - Name change for post inc operands

Pull Request - State: closed - Opened by MaryBennett over 1 year ago - 2 comments

#62 - Post inc fixes

Pull Request - State: closed - Opened by MaryBennett over 1 year ago - 3 comments

#61 - latest released (02/Aug) gcc toolchain generates incorrect code.

Issue - State: closed - Opened by superflyers over 1 year ago - 2 comments

#60 - Update naming for xcvmem instructions

Issue - State: closed - Opened by MaryBennett over 1 year ago - 3 comments

#59 - Fixed operand order for xcvbitmanip instructions

Pull Request - State: closed - Opened by MaryBennett over 1 year ago - 2 comments

#58 - Post-inc memory access generation for -Os -Oz and -Og

Issue - State: closed - Opened by jeremybennett over 1 year ago - 6 comments
Labels: enhancement

#56 - CORE-V: All instructions in builtins are currently using lowercase

Issue - State: closed - Opened by NandniJamnadas over 1 year ago - 1 comment

#55 - Getting CORE-V ready for Upstream

Issue - State: open - Opened by NandniJamnadas over 1 year ago - 4 comments
Labels: enhancement

#53 - CORE-V: SIMD Constraints "CV6" and "CS6" needs renaming

Issue - State: closed - Opened by NandniJamnadas over 1 year ago - 3 comments

#52 - CORE-V: SIMD Update: cv.avgu.sc{i}[.h,.b] builtins from signed to uns…

Pull Request - State: closed - Opened by NandniJamnadas over 1 year ago - 2 comments

#50 - CORE-V: SIMD Update: Updated cv.pack and cv.pack.h builtins

Pull Request - State: closed - Opened by NandniJamnadas over 1 year ago

#48 - How should IDEs gain awareness of Builtins?

Issue - State: closed - Opened by NandniJamnadas over 1 year ago - 3 comments

#47 - CORE-V: Bit Manipulation bitrev builtin update

Pull Request - State: closed - Opened by NandniJamnadas over 1 year ago - 1 comment

#46 - CORE-V: Event Load Builtin Update

Pull Request - State: closed - Opened by NandniJamnadas over 1 year ago

#45 - CORE-V: Remove versioning support for XCV Extensions

Pull Request - State: closed - Opened by NandniJamnadas over 1 year ago - 1 comment

#44 - Backport CORE-V fast interrupts

Pull Request - State: closed - Opened by craigblackmore over 1 year ago - 1 comment

#43 - CORE-V: Fix typo in mac/msu tests

Pull Request - State: closed - Opened by craigblackmore over 1 year ago - 1 comment

#42 - CORE-V: Support CORE-V fast interrupts

Pull Request - State: closed - Opened by craigblackmore over 1 year ago - 2 comments

#41 - Autogenerate for mac and msu builtins

Pull Request - State: closed - Opened by urekhun over 1 year ago - 1 comment

#40 - __builtin_riscv_cv_bitmanip_insert generate incorrect operand

Issue - State: closed - Opened by superflyers over 1 year ago - 7 comments
Labels: bug

#39 - Builtins Implementation Status compared to LLVM

Issue - State: open - Opened by NandniJamnadas over 1 year ago - 3 comments

#38 - CV32E40Pv2 Immediate Branch Auto-Generation Support

Pull Request - State: closed - Opened by NandniJamnadas over 1 year ago - 1 comment

#37 - GCC requires version number to be specified with architecture extensions

Issue - State: closed - Opened by jeremybennett over 1 year ago - 2 comments
Labels: bug

#36 - Extensions state save and restore

Issue - State: open - Opened by pascalgouedo over 1 year ago - 6 comments
Labels: bug

#35 - ra register is modified when Zcmp enabled

Issue - State: closed - Opened by bigmagic123 almost 2 years ago - 2 comments

#34 - CV32E40Pv2 General ALU Builtins Update

Pull Request - State: closed - Opened by NandniJamnadas almost 2 years ago - 1 comment

#33 - Update operand order to match spec for bit manip instructions

Pull Request - State: closed - Opened by MaryBennett almost 2 years ago - 2 comments

#32 - Conflict between spec and GCC of bit manipulation instructions

Issue - State: closed - Opened by melonedo almost 2 years ago - 2 comments

#31 - __builtin_riscv_cv_alu_addRN() builtin generate incorrect assemble operand

Issue - State: closed - Opened by superflyers almost 2 years ago - 2 comments
Labels: bug

#30 - Attribute interrupt causes register corruption when Zcmp enabled

Issue - State: closed - Opened by Wren6991 almost 2 years ago - 3 comments
Labels: bug

#29 - XCVALU builtins added

Pull Request - State: closed - Opened by urekhun almost 2 years ago - 3 comments

#28 - Removed Implicit ISA info for CORE-V

Pull Request - State: closed - Opened by NandniJamnadas almost 2 years ago - 2 comments

#27 - CV32E40Pv2 Event Load Update

Pull Request - State: closed - Opened by NandniJamnadas almost 2 years ago - 1 comment

#26 - How should an out-of-range index be treated?

Issue - State: closed - Opened by melonedo almost 2 years ago - 3 comments

#25 - Remove 'xcv' extension

Pull Request - State: closed - Opened by CharKeaney almost 2 years ago - 2 comments

#24 - Update CORE-V Extension name prefix from 'xcorev' to 'xcv'

Pull Request - State: closed - Opened by CharKeaney almost 2 years ago - 2 comments

#23 - CV32E40Pv2 CORE-V SIMD Update

Pull Request - State: closed - Opened by NandniJamnadas almost 2 years ago - 2 comments

#22 - Builtin optimisation enhancement

Issue - State: open - Opened by MaryBennett almost 2 years ago - 2 comments
Labels: enhancement

#21 - XCOREVBITMANIP builtins added

Pull Request - State: closed - Opened by MaryBennett almost 2 years ago

#20 - Zcmp CFI may need fixing

Issue - State: closed - Opened by jeremybennett almost 2 years ago - 1 comment
Labels: bug

#19 - CV32E40Pv2 220 CORE-V SIMD Builtins Version 1

Pull Request - State: closed - Opened by NandniJamnadas about 2 years ago - 1 comment

#18 - XCOREVMAC builtins added

Pull Request - State: closed - Opened by MaryBennett about 2 years ago - 2 comments

#17 - DWARF error: mangled line number section

Issue - State: closed - Opened by tovine about 2 years ago - 3 comments
Labels: bug

#14 - Event Load Builtin needs documenting

Issue - State: closed - Opened by jeremybennett about 2 years ago - 1 comment
Labels: bug

#13 - CV32E40Pv2 Event Load Builtin

Pull Request - State: closed - Opened by NandniJamnadas about 2 years ago - 2 comments