Ecosyste.ms: Issues

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GitHub / ni/niveristand-fpga-addon-custom-device issues and pull requests

#100 - Update FPGA Register IO library

Pull Request - State: closed - Opened by zszilagy over 3 years ago - 11 comments

#100 - Update FPGA Register IO library

Pull Request - State: closed - Opened by zszilagy over 3 years ago - 11 comments

#99 - Doc Update for Feature 1206272

Pull Request - State: closed - Opened by WillCawley over 3 years ago - 1 comment

#99 - Doc Update for Feature 1206272

Pull Request - State: closed - Opened by WillCawley over 3 years ago - 1 comment

#98 - Implement register write unit tests

Pull Request - State: closed - Opened by zszilagy over 3 years ago - 22 comments

#97 - Add issues templates

Pull Request - State: closed - Opened by PaulDanH over 3 years ago

#96 - Error 56 in VS 2019 (Linux and PharLap)

Issue - State: closed - Opened by Brian-Kindinger almost 4 years ago - 4 comments

#95 - Examples Installation BugFix

Pull Request - State: closed - Opened by DStavilaNI almost 4 years ago - 7 comments

#94 - FPGA Register IO - Read testing

Pull Request - State: closed - Opened by DStavilaNI almost 4 years ago - 47 comments

#93 - Created unit test infrastructure and test example

Pull Request - State: closed - Opened by zszilagy almost 4 years ago - 1 comment

#92 - FPGA Register IO library

Pull Request - State: closed - Opened by DStavilaNI almost 4 years ago

#91 - Added the libraries along with the template VIs to the FPGA Addon Project (FXP Support)

Pull Request - State: closed - Opened by zszilagy almost 4 years ago - 3 comments

#90 - Added the libraries along with the template VIs to the FPGA Addon Project (FXP Support)

Pull Request - State: closed - Opened by zszilagy almost 4 years ago - 5 comments

#89 - System Explorer BugFix - Handling naming conflicts

Pull Request - State: closed - Opened by DStavilaNI almost 4 years ago - 2 comments

#88 - Fix typos in Context Help of Import FPGA Addon Configuration.vi

Pull Request - State: closed - Opened by PaulDanH almost 4 years ago - 1 comment

#87 - Changed the RIO address off the FPGA Addon CD from RIO0 to RIO1

Pull Request - State: closed - Opened by zszilagy almost 4 years ago

#85 - Fixed the bug where the speciality IO channels got broken on reloading the bitfile

Pull Request - State: closed - Opened by zszilagy almost 4 years ago - 6 comments

#84 - Context Help Documentation Update

Pull Request - State: closed - Opened by DStavilaNI almost 4 years ago - 1 comment

#82 - Fix size and alignment for refresh bitfile button.

Pull Request - State: closed - Opened by PaulDanH almost 4 years ago - 2 comments

#81 - Documentation update - BugFIX with Github displayed images

Pull Request - State: closed - Opened by DStavilaNI almost 4 years ago

#80 - Add unit and system level tests to validate the "Reload Bitfile" feature

Pull Request - State: closed - Opened by zszilagy almost 4 years ago - 8 comments

#79 - Added handler for bitpacked scalar data type change

Pull Request - State: closed - Opened by zszilagy almost 4 years ago - 3 comments

#78 - Documentation and Public API Controls updated

Pull Request - State: closed - Opened by DStavilaNI almost 4 years ago - 2 comments

#77 - Added installer for the FPGA Addon Scripting API Examples

Pull Request - State: closed - Opened by zszilagy almost 4 years ago

#76 - Update FPGA Addon Quick Start Guide.md

Pull Request - State: closed - Opened by WillCawley almost 4 years ago - 2 comments

#75 - ScriptinAPI_Examples

Pull Request - State: closed - Opened by DStavilaNI almost 4 years ago - 1 comment

#74 - SE BugFix and Quick Start Guide update

Pull Request - State: closed - Opened by DStavilaNI about 4 years ago - 1 comment

#73 - Documentation

Pull Request - State: closed - Opened by DStavilaNI about 4 years ago - 1 comment

#72 - FPGA Addon Scripting API - Icons update

Pull Request - State: closed - Opened by DStavilaNI about 4 years ago - 2 comments

#71 - Refactoring for the Scalar and Waveform channels

Pull Request - State: closed - Opened by DStavilaNI about 4 years ago - 2 comments

#70 - Refactored the 'Get Active Scalar Section.vi'

Pull Request - State: closed - Opened by zszilagy about 4 years ago - 14 comments

#69 - Fixed the issue regarding the incorrect FPGA Addon version number

Pull Request - State: closed - Opened by zszilagy about 4 years ago

#68 - Added unit tests for the bitfile reload functionality.

Pull Request - State: closed - Opened by zszilagy about 4 years ago - 12 comments

#67 - Added unit test to validate Delete FPGA Addon scripting API node

Pull Request - State: closed - Opened by zszilagy about 4 years ago - 3 comments

#66 - Add unit test for "Delete FPGA Addon" scripting node

Pull Request - State: closed - Opened by zszilagy about 4 years ago - 3 comments

#65 - Implement bitfile reload functionality

Pull Request - State: closed - Opened by zszilagy about 4 years ago - 10 comments

#64 - FPGA Addon Scripting API - Bugfixes

Pull Request - State: closed - Opened by DStavilaNI about 4 years ago - 4 comments

#63 - FPGA Addon Scripting API - Unit Tests

Pull Request - State: closed - Opened by DStavilaNI about 4 years ago - 4 comments

#62 - FPGA Addon Scripting API - Unit Tests

Pull Request - State: closed - Opened by DStavilaNI about 4 years ago - 8 comments

#61 - FPGA Addon Scripting API - Create FPGA Addon & Find FPGA Addon Unit Tests

Pull Request - State: closed - Opened by DStavilaNI about 4 years ago - 10 comments

#59 - Create FPGA addon scripting api installer

Pull Request - State: closed - Opened by zszilagy about 4 years ago

#58 - Added the "Refresh bitfile functionality to the FPGA Addon Custom device

Pull Request - State: closed - Opened by zszilagy about 4 years ago - 26 comments

#57 - Scripting API - Implementation

Pull Request - State: closed - Opened by DStavilaNI about 4 years ago - 27 comments

#56 - Update FPGA Addon Quick Start Guide.md

Pull Request - State: closed - Opened by WillCawley over 4 years ago

#55 - Fixed naming issue in suggested items list (#54)

Pull Request - State: closed - Opened by zszilagy over 4 years ago

#53 - Fixed paths to example snips in README files

Pull Request - State: closed - Opened by csteavu over 4 years ago

#51 - Added example references to quick start guide

Pull Request - State: closed - Opened by csteavu over 4 years ago

#49 - Create examples

Pull Request - State: closed - Opened by csteavu over 4 years ago - 13 comments

#47 - Fix NI-RIO version in README

Pull Request - State: closed - Opened by bogdanp-ni over 4 years ago

#46 - Removed the Custom Device folder from the built path

Pull Request - State: closed - Opened by zszilagy over 4 years ago

#45 - Added the FPGA Addon System Defintion API.lvproj with all its dependencies to the repo

Pull Request - State: closed - Opened by zszilagy over 4 years ago - 1 comment

#43 - Changed the "VeriStand" to "NIVeriStand" in the Custom Device FPGA Addon.xml (ni-rt path)

Pull Request - State: closed - Opened by zszilagy over 4 years ago - 1 comment

#42 - Added logic to ignore error 63186 as it is outdated

Pull Request - State: closed - Opened by csteavu over 4 years ago - 1 comment

#40 - Modified the CD Storage Library Load.vi, so it also includes LV2020 version

Pull Request - State: closed - Opened by zszilagy over 4 years ago - 2 comments

#39 - Changed the Maintainer from National Instruments to NI

Pull Request - State: closed - Opened by zszilagy over 4 years ago

#38 - FPGA Addon CD - Adding the FPGA Specialty IOs library as a submodule dependency

Pull Request - State: closed - Opened by DStavilaNI over 4 years ago - 2 comments

#37 - Preparation for deployment and test runs on the ATS machine - Part 2

Pull Request - State: closed - Opened by DStavilaNI over 4 years ago - 1 comment

#36 - Preparation for deployment and test runs on the ATS machine

Pull Request - State: closed - Opened by DStavilaNI over 4 years ago

#35 - Migration of all the System Test Assets to the ATS HW configuration

Pull Request - State: closed - Opened by DStavilaNI over 4 years ago - 19 comments

#34 - Add generic unit tests

Pull Request - State: closed - Opened by PaulDanH over 4 years ago - 1 comment

#33 - Renamed Test Classes and Remove Max Nr of Channels Test Class

Pull Request - State: closed - Opened by PaulDanH over 4 years ago

#32 - FPGA Addon CD - Backport to LabVIEW 2018

Pull Request - State: closed - Opened by DStavilaNI over 4 years ago

#31 - [DRAFT PR]Modified the path to the VeriStandTestCase.lvclass

Pull Request - State: closed - Opened by zszilagy over 4 years ago

#30 - Created System Level Tests for the FPGA Addon Status Channels

Pull Request - State: closed - Opened by zszilagy over 4 years ago - 8 comments

#29 - DMA Channels Interleaved Testing

Pull Request - State: closed - Opened by DStavilaNI over 4 years ago - 18 comments

#28 - Update build label for new server

Pull Request - State: closed - Opened by buckd over 4 years ago

#27 - Unit Tests for Adding channel items

Pull Request - State: closed - Opened by PaulDanH over 4 years ago - 5 comments

#26 - Migration of Quick Start Documentation from HTML to Markdown

Pull Request - State: closed - Opened by DStavilaNI over 4 years ago - 2 comments

#25 - Refactor DMA Channels.vi and write unit tests which validates the funcitonality

Pull Request - State: closed - Opened by zszilagy over 4 years ago - 5 comments

#24 - Refactor DMA Channel.vi

Pull Request - State: closed - Opened by zszilagy over 4 years ago - 6 comments

#23 - System Level Tests for basic DMA Channels Testing

Pull Request - State: closed - Opened by DStavilaNI over 4 years ago - 13 comments

#22 - Added Bitfile Parsing unit tests and Max Nr of Scalar channels system test

Pull Request - State: closed - Opened by csteavu over 4 years ago - 15 comments

#21 - FPGA Addon (DMA) Waveform Channels Tests -> Draft Pull Request

Pull Request - State: closed - Opened by DStavilaNI over 4 years ago - 2 comments

#20 - Fixed the lvclass conflict caused by moving the vi's on the disk

Pull Request - State: closed - Opened by zszilagy over 4 years ago - 1 comment

#19 - Added FPGA-Addon-Specialty-IO submodule

Pull Request - State: closed - Opened by zszilagy over 4 years ago

#17 - Update package name, architecture, license

Pull Request - State: closed - Opened by rtzoeller over 4 years ago - 1 comment

#16 - Merge fix from original repo for the error message when first adding FPGA Addon

Pull Request - State: closed - Opened by PaulDanH over 4 years ago - 1 comment

#15 - FPGA CD - Scalar Channels Testing

Pull Request - State: closed - Opened by DStavilaNI over 4 years ago - 18 comments

#14 - dummy test PR, will be deleted

Pull Request - State: closed - Opened by bogdanp-ni over 4 years ago

#12 - Fixed the apostrophe type in Jenkinsfile

Pull Request - State: closed - Opened by zszilagy over 4 years ago

#11 - Updated build spec paths, build.toml and Jenkinsfile

Pull Request - State: closed - Opened by zszilagy over 4 years ago

#10 - Update Jenkinsfile to include diffPipeline

Pull Request - State: closed - Opened by PaulDanH over 4 years ago

#9 - Refactoring for Add Item.vi in Write/Read Waveform Case

Pull Request - State: closed - Opened by PaulDanH over 4 years ago - 3 comments

#8 - Updated the build.toml and jenkinsfile

Pull Request - State: closed - Opened by zszilagy over 4 years ago

#7 - Cleanup README.md to be more in sync with other CDs

Pull Request - State: closed - Opened by PaulDanH over 4 years ago

#6 - Update LICENSE file

Pull Request - State: closed - Opened by PaulDanH over 4 years ago

#5 - Add PULL_REQUEST_TEMPLATE.md file

Pull Request - State: closed - Opened by PaulDanH over 4 years ago

#4 - Add contributing.md file

Pull Request - State: closed - Opened by PaulDanH over 4 years ago

#3 - Add contributing.md file

Pull Request - State: closed - Opened by PaulDanH over 4 years ago