myhdl/myhdl issues and pull requests

#441 - New release or new version to pypi?

Issue - State: closed - Opened by TurnOffNOD 27 days ago - 2 comments
Labels: enhancement

#440 - Asynchronous reset with and ResetSignal(in vhdl)

Issue - State: open - Opened by 0TulipRose0 about 2 months ago - 1 comment

#439 - blocked initialization of TristateSignals

Pull Request - State: closed - Opened by josyb about 2 months ago

#438 - Error when converting a a tri state signal to VHDL

Issue - State: closed - Opened by tobygomersall about 2 months ago - 6 comments
Labels: bug

#437 - Tests are not passing?

Issue - State: closed - Opened by Kreijstal about 2 months ago - 4 comments

#435 - Enhance README: Shields to capture the attention of potential contributors

Pull Request - State: closed - Opened by devactivity-team 3 months ago - 2 comments

#434 - Inconsistent behavior of assignment of Signal(intbv()[w:]) to Signal(bool())

Issue - State: open - Opened by josyb 3 months ago - 2 comments
Labels: help wanted

#433 - _toVerilog.py: 'skip_zero_mem_init': repaired test for 'zero' value :(

Pull Request - State: closed - Opened by josyb 4 months ago - 1 comment

#432 - _toVerilog.py: 'skip_zero_mem_init': added forgotten condition

Pull Request - State: closed - Opened by josyb 4 months ago - 1 comment

#431 - _toVerilog.py: expanding `initial_values` kwarg to add 'skip_zero_mem…

Pull Request - State: closed - Opened by josyb 4 months ago - 1 comment

#430 - Removed support for Python 3.7 (which is End Of Life since 2023-06-27)

Pull Request - State: closed - Opened by josyb 7 months ago - 7 comments

#429 - Bit indexing may cause deprecation warnings

Issue - State: open - Opened by zhijieshi 8 months ago - 9 comments

#428 - Init list of enums

Pull Request - State: closed - Opened by josyb 8 months ago

#427 - Change how windows does pip install (again)

Pull Request - State: closed - Opened by davekeeshan 8 months ago

#426 - List of enums, vcd representation, pck_myhdl_xx version

Pull Request - State: closed - Opened by josyb 8 months ago - 1 comment

#425 - Code generation working on python 3.6 but not 3.11

Issue - State: closed - Opened by bjohan 9 months ago - 2 comments

#424 - OpenPort for unused outputs

Pull Request - State: closed - Opened by josyb 12 months ago

#423 - Constant signals

Pull Request - State: closed - Opened by josyb 12 months ago - 1 comment

#422 - Fix pip install on windows

Pull Request - State: closed - Opened by davekeeshan 12 months ago

#421 - Patch analyze.py to not mangle toplevel names

Pull Request - State: closed - Opened by ThomasHornschuh about 1 year ago - 1 comment

#420 - is it possible to write a testbench.vcd from Cosimulation(...)?

Issue - State: closed - Opened by olisnr over 1 year ago - 6 comments

#419 - cosimulation

Issue - State: closed - Opened by olisnr over 1 year ago - 2 comments

#417 - doc: added expalantion of how reset operates on ListOfSignals

Pull Request - State: closed - Opened by josyb over 1 year ago

#416 - verilog and VHDL reset from @allways_seq() is strange

Issue - State: closed - Opened by olisnr over 1 year ago - 9 comments
Labels: question

#415 - Updating README.md to show alternative solutions to install MyHDL

Pull Request - State: closed - Opened by josyb over 1 year ago

#414 - different python versions

Issue - State: open - Opened by olisnr over 1 year ago - 14 comments
Labels: question

#413 - website defekt installaion link ' missing...

Issue - State: closed - Opened by olisnr over 1 year ago
Labels: question

#412 - Cleaning up tests:

Pull Request - State: closed - Opened by josyb over 1 year ago - 4 comments

#411 - Error: myhdl.AlwaysCombError: sensitivity list is empty

Issue - State: closed - Opened by IamJezza over 1 year ago - 4 comments
Labels: question

#410 - Add windows actions, python3.11 for core and ghdl

Pull Request - State: closed - Opened by davekeeshan over 1 year ago

#409 - verify_convert() doesn't appear to work as expected

Issue - State: open - Opened by davekeeshan over 1 year ago - 3 comments
Labels: bug

#408 - True case statment mapping support

Pull Request - State: closed - Opened by davekeeshan over 1 year ago - 1 comment

#407 - Constant value inversion (~0x1, ~0x4523) not working in VHDL

Pull Request - State: closed - Opened by davekeeshan over 1 year ago

#406 - Python3.7 Deprecation list

Issue - State: open - Opened by davekeeshan over 1 year ago - 11 comments
Labels: bug

#405 - Constant value inversion (~0x1, ~0x4523) not working in VHDL

Issue - State: closed - Opened by davekeeshan over 1 year ago - 8 comments
Labels: bug

#404 - Binops convert in VHDL fix

Pull Request - State: closed - Opened by davekeeshan over 1 year ago

#403 - BinOps failing if unsigned assigned to boolean in VHDL

Issue - State: closed - Opened by davekeeshan over 1 year ago - 1 comment
Labels: bug

#401 - Raise traceSignals to DeprecationWarning from UserWarning

Pull Request - State: closed - Opened by davekeeshan almost 2 years ago - 4 comments

#400 - Release 0.11.42

Pull Request - State: closed - Opened by josyb almost 2 years ago

#399 - Clean PyPi release flow 17/12/2022

Pull Request - State: closed - Opened by davekeeshan almost 2 years ago - 4 comments

#398 - Add reverse updated to Github actions

Pull Request - State: open - Opened by davekeeshan almost 2 years ago - 7 comments

#397 - Review Tests Investigate all marked xfail

Issue - State: open - Opened by davekeeshan almost 2 years ago

#396 - Update makeflow

Pull Request - State: closed - Opened by davekeeshan almost 2 years ago

#393 - Migrate PyPi release to github actions

Issue - State: open - Opened by davekeeshan almost 2 years ago - 6 comments
Labels: enhancement

#389 - Fixes issue #388 incorrect conversion of `elif siga == expression`

Pull Request - State: open - Opened by josyb almost 2 years ago - 1 comment

#388 - verliog generation of constants is strange

Issue - State: closed - Opened by olisnr almost 2 years ago - 10 comments
Labels: bug

#387 - Update flow to compile and used cached version of GHDL/Icarus

Pull Request - State: closed - Opened by davekeeshan almost 2 years ago

#386 - Support for switch in MyHDL

Issue - State: open - Opened by davekeeshan almost 2 years ago - 4 comments
Labels: enhancement

#385 - Dynamic Variable assignment

Issue - State: open - Opened by davekeeshan almost 2 years ago - 9 comments
Labels: bug, conversion

#384 - User Defined code not working (verilog_code/vhdl_code)

Issue - State: open - Opened by davekeeshan almost 2 years ago - 9 comments
Labels: enhancement

#383 - Fix a typo in an error message - integeer -> integer

Pull Request - State: closed - Opened by jtremesay almost 2 years ago

#382 - add python 3.11 to ci matrix

Pull Request - State: closed - Opened by jck almost 2 years ago - 1 comment

#381 - Reduce memory footprint

Pull Request - State: open - Opened by telemarkguru almost 2 years ago - 10 comments

#380 - Added missing visit_NameConstant() for Python versions 3.7 and 3.8

Pull Request - State: closed - Opened by josyb almost 2 years ago

#379 - ‘Constant’ object has no attribute 'signed'

Issue - State: closed - Opened by BlackJackJam almost 2 years ago - 5 comments

#378 - how to properly create a (synthesized) parity checker function

Issue - State: open - Opened by rafaelcorsi about 2 years ago - 1 comment
Labels: question

#377 - always_comb sensitivity list is Empty

Issue - State: closed - Opened by PiyushSaini09 about 2 years ago - 4 comments
Labels: question

#376 - Removed testing with Python 3.6 - EOL <> Added testing with PyPy 3.9

Pull Request - State: closed - Opened by josyb about 2 years ago

#375 - SystemVerilog support

Pull Request - State: closed - Opened by josyb about 2 years ago - 1 comment

#374 - vhdl wrong resize length on port

Issue - State: closed - Opened by rafaelcorsi about 2 years ago - 3 comments

#373 - AttributeError: 'Name' object has no attribute 'value'

Issue - State: open - Opened by Grissess about 2 years ago - 9 comments

#372 - Incorrect translation in comparation

Issue - State: open - Opened by Pusiol over 2 years ago - 3 comments
Labels: bug

#371 - [ENH] Updated the ConcatSignal conversion code to check for undriven …

Pull Request - State: closed - Opened by tobygomersall over 2 years ago - 3 comments

#370 - create infinit delay with delay(-1)

Issue - State: closed - Opened by rafaelcorsi over 2 years ago - 1 comment

#369 - Setup github actions

Pull Request - State: closed - Opened by davekeeshan over 2 years ago

#368 - removed error on reading back outputs of `always_comb` process

Pull Request - State: closed - Opened by josyb over 2 years ago

#367 - shift_left conversion issue in vhdl

Issue - State: open - Opened by davekeeshan over 2 years ago - 46 comments
Labels: bug

#366 - config_sim tracebackup undocumented

Issue - State: closed - Opened by rafaelcorsi over 2 years ago - 1 comment
Labels: bug

#365 - fix typo on structure doc

Pull Request - State: closed - Opened by rafaelcorsi over 2 years ago

#364 - ConcatSignal misbehavior converting to hdl

Issue - State: open - Opened by rafaelcorsi over 2 years ago - 2 comments

#363 - update mux2 example to python3 (print)

Pull Request - State: closed - Opened by rafaelcorsi over 2 years ago

#362 - Added support for lists in ports

Pull Request - State: open - Opened by lucasasselli over 2 years ago - 5 comments

#361 - Could you help to check if here is non-blocking or blocking?

Issue - State: open - Opened by TarzanPan over 3 years ago - 1 comment
Labels: question

#360 - Modelsim vlog vcom and vsim clarification

Issue - State: open - Opened by dmitrii-galantsev over 3 years ago

#359 - Conversion with recursive ShadowSignals

Pull Request - State: closed - Opened by josyb over 3 years ago - 3 comments

#358 - Fixing issue #350

Pull Request - State: closed - Opened by josyb over 3 years ago

#357 - Removed 'casez' in Verilog onehot / onecold state encoding

Pull Request - State: closed - Opened by josyb over 3 years ago - 16 comments

#356 - One-hot state machine conversion to Verilog

Issue - State: open - Opened by kc64 over 3 years ago
Labels: bug

#355 - replace yield_fixture decorator by fixture

Pull Request - State: closed - Opened by hellow554 over 3 years ago - 1 comment

#354 - conda-forge package

Issue - State: open - Opened by davidbrochart over 3 years ago - 1 comment
Labels: documentation

#353 - Fix documentation links for Issue #352

Pull Request - State: closed - Opened by venks1 over 3 years ago

#352 - MEP links in documentation point to old doku locations

Issue - State: closed - Opened by venks1 over 3 years ago - 1 comment
Labels: bug

#351 - Fix for issue #348 (traceSignals incorrectly writes real value signal to VCD)

Pull Request - State: open - Opened by NicoPy almost 4 years ago - 1 comment

#350 - Conversion failing with Python 3.9

Issue - State: closed - Opened by cfelton almost 4 years ago - 17 comments
Labels: bug

#349 - Verilog Conversion could handle tuples of quantities convertible to ints

Issue - State: open - Opened by venks1 almost 4 years ago - 8 comments
Labels: bug

#348 - traceSignals incorrectly writes real value signal to VCD

Issue - State: open - Opened by zlobriy almost 4 years ago - 11 comments
Labels: bug

#347 - Use first value instead of -1 as index in for loops

Pull Request - State: open - Opened by benzea about 4 years ago - 3 comments

#346 - Asynchronous Reset but not every FF, VHDL

Issue - State: open - Opened by LarsRlrs about 4 years ago - 19 comments
Labels: bug

#345 - Init reset fix

Pull Request - State: closed - Opened by ThomasHornschuh about 4 years ago - 2 comments

#344 - how to assign input variable to weights of a neural network

Issue - State: open - Opened by LavanyaMa about 4 years ago - 2 comments

#343 - ConversionError: non-boolean argument in logical operator

Issue - State: closed - Opened by LavanyaMa over 4 years ago - 2 comments

#342 - Update _toVerilog.py

Pull Request - State: closed - Opened by TongJoe over 4 years ago - 3 comments

#341 - verilog code conversion not showing in the respective folder

Issue - State: closed - Opened by LavanyaMa over 4 years ago - 15 comments

#340 - Update VCD support for real numbers

Issue - State: open - Opened by capacollo over 4 years ago
Labels: enhancement

#339 - Exercising "test_tristate.py"

Pull Request - State: closed - Opened by josyb over 4 years ago - 4 comments

#338 - Added cosimulation with verilator v4 and https://github.com/csail-csg/pyverilator

Pull Request - State: open - Opened by joshuisken over 4 years ago - 3 comments

#337 - add more docs details to instances()

Pull Request - State: closed - Opened by raczben over 4 years ago

#336 - No more name mangling

Pull Request - State: closed - Opened by josyb over 4 years ago - 23 comments

#335 - github actions

Pull Request - State: closed - Opened by jck over 4 years ago - 1 comment

#334 - move CI from travis to github actions

Issue - State: closed - Opened by jck over 4 years ago - 2 comments
Labels: enhancement

GitHub / myhdl/myhdl issues and pull requests