m-labs/nmigen issues and pull requests

#350 - For loops in Nmigen

Issue - State: open - Opened by ParasVekariya almost 3 years ago

#349 - No clk being generated

Issue - State: open - Opened by mayank-kabra2001 over 3 years ago

#348 - nmigen install error

Issue - State: closed - Opened by ZhangPeterGree almost 4 years ago - 1 comment

#347 - Does nmigen support I2C master ?

Issue - State: closed - Opened by jimmymagemtek about 4 years ago - 1 comment

#346 - Want to know some details of the back

Issue - State: open - Opened by ekikun over 4 years ago - 1 comment

#345 - Improve readability of assignments and add contexts for clock domains

Issue - State: open - Opened by ildus over 4 years ago

#344 - Update UART Example so that acknowledging RX data sets RX ready low.

Pull Request - State: open - Opened by newhouseb over 4 years ago

#343 - Fix broken timing constraints

Pull Request - State: closed - Opened by slan over 4 years ago

#342 - Please add details that this repository is obsolete/not longer maintained anymore for new comer

Issue - State: closed - Opened by bvernoux over 4 years ago - 3 comments

#341 - Python simulator hangs or throws when trying to drive reset from testbench

Issue - State: closed - Opened by hansfbaier over 4 years ago - 1 comment

#340 - negative values support in Switch-Case

Issue - State: closed - Opened by weshu over 4 years ago - 1 comment

#339 - Add variable keyword argument support to nmigen.hdl.rec.Record

Pull Request - State: open - Opened by DonaldKellett almost 5 years ago

#338 - Add option to specify spec_name

Pull Request - State: closed - Opened by DonaldKellett almost 5 years ago

#337 - Add option to specify solver in nmigen.test.utils

Pull Request - State: closed - Opened by DonaldKellett about 5 years ago

#336 - Allow more flexibility in FHDLTestCase assertFormal

Issue - State: closed - Opened by DonaldKellett about 5 years ago

#335 - Convert tests to regex versions

Pull Request - State: closed - Opened by grvvy about 5 years ago

#334 - Add initial support for Symbiflow toolchain for Xilinx 7-series

Pull Request - State: closed - Opened by mglb about 5 years ago

#334 - Add initial support for Symbiflow toolchain for Xilinx 7-series

Pull Request - State: closed - Opened by mglb about 5 years ago

#333 - Signal decoder inference for Enums doesn't work for Layout members

Issue - State: open - Opened by shawnanastasio over 5 years ago

#332 - Can't generate verilog for blinky example: Only signals may be added as ports

Issue - State: closed - Opened by shawnanastasio over 5 years ago - 1 comment

#331 - lambdasoc analysis & synthesis got error on intel platform.

Issue - State: open - Opened by franz-git over 5 years ago

#330 - Fixes FileNotFoundError that happens when running formal proofs

Pull Request - State: closed - Opened by colepoirier over 5 years ago

#329 - Generating async negedge reset

Issue - State: open - Opened by tariqafzal over 5 years ago

#328 - Hierarchical Redundancy in emitted Verilog

Issue - State: open - Opened by BracketMaster over 5 years ago - 1 comment

#327 - Can I create an active-low (asynchronous) reset?

Issue - State: closed - Opened by hofstee over 5 years ago

#326 - Fix `_yosys_version()`

Pull Request - State: closed - Opened by hofstee over 5 years ago - 1 comment

#325 - Bus arbiter broken after synthesis

Issue - State: closed - Opened by strobo5 over 5 years ago - 1 comment

#324 - use declarative setuptools config

Pull Request - State: closed - Opened by graingert over 5 years ago

#323 - Installation fails if wheel not installed

Issue - State: open - Opened by alanvgreen over 5 years ago - 3 comments

#322 - Release timeline

Issue - State: closed - Opened by FFY00 over 5 years ago - 2 comments

#321 - Internal Oscillator Usage ICE40

Issue - State: closed - Opened by jchidley over 5 years ago - 7 comments

#320 - Unable to Build and flash my board.

Issue - State: closed - Opened by teezzan over 5 years ago - 9 comments

#319 - Index a signal with a slice from another signal

Issue - State: closed - Opened by rnd2 over 5 years ago - 2 comments

#318 - Initial Class: ValueError: call stack is not deep enough

Issue - State: closed - Opened by goktug97 over 5 years ago - 4 comments

#317 - Using Python to Formal Verify Verilog and VHDL Files

Issue - State: closed - Opened by goktug97 over 5 years ago - 4 comments

#316 - Case pattern syntax improvement

Issue - State: closed - Opened by porglezomp over 5 years ago - 2 comments

#315 - FSM with transition to nonexistent state should not elaborate

Issue - State: closed - Opened by awygle over 5 years ago - 1 comment

#314 - How to pass yosys_opts to LatticeICE40Platform?

Issue - State: closed - Opened by RobertBaruch over 5 years ago - 2 comments

#313 - build.dsl: allow strings to be used as connector numbers

Pull Request - State: closed - Opened by anuejn over 5 years ago - 3 comments

#312 - Assignment to a Record with zero-width fields generates invalid Verilog

Issue - State: closed - Opened by jfng over 5 years ago - 3 comments
Labels: bug, backend:RTLIL

#311 - Support for non integer connector / ressource 'numbers'

Issue - State: closed - Opened by anuejn over 5 years ago - 2 comments
Labels: feature

#310 - hdl.ast.Value.word_select() works incorrectly on actual platform (ECP5 Versa)

Issue - State: open - Opened by ghost over 5 years ago - 5 comments
Labels: bug

#309 - vendor.lattice_{ice40,ecp5}: Support .il (RTLIL) files in extra_files

Pull Request - State: closed - Opened by smunaut over 5 years ago - 1 comment

#308 - Support Platforms that include an existing design and expose interface to that design as Resource

Issue - State: open - Opened by smunaut over 5 years ago
Labels: feature

#307 - AssertionError domain.name not in self.domains

Issue - State: closed - Opened by nicolas-robin over 5 years ago - 4 comments

#306 - vendor.lattice_ecp5: Support internal oscillator (OSCG)

Pull Request - State: closed - Opened by miek over 5 years ago - 2 comments

#305 - AssertionError with strange Switch

Issue - State: closed - Opened by Ravenslofty over 5 years ago - 1 comment
Labels: bug

#304 - ResetSynchronizer clockdomain in submodule is not renamed properly with multiple submodule instances

Issue - State: closed - Opened by povauboin over 5 years ago - 3 comments
Labels: bug

#303 - Usability? Can we warn if a Statement is never assigned to a domain?

Issue - State: closed - Opened by RobertBaruch over 5 years ago - 2 comments
Labels: improvement

#302 - nmigen generates invalid RTLIL with negative shifts

Issue - State: closed - Opened by Ravenslofty over 5 years ago - 1 comment
Labels: bug, backend:RTLIL

#301 - vendor.xilinx_7series: Vivado TIMING-2 Warning

Issue - State: closed - Opened by peteut over 5 years ago - 4 comments
Labels: improvement, platform:xilinx-7series

#300 - Intel altiobuf_ requires oe with the same with as data lines.

Pull Request - State: closed - Opened by schwigi over 5 years ago - 2 comments

#299 - build.run: fix indentation.

Pull Request - State: closed - Opened by peteut over 5 years ago - 1 comment

#298 - back.verilog: honour write_verilog_opts.

Pull Request - State: closed - Opened by peteut over 5 years ago - 4 comments

#297 - Output enable for Intel platform on multi I/O pins

Issue - State: closed - Opened by schwigi over 5 years ago - 6 comments
Labels: bug, platform:intel

#296 - Signal: allow to use integral Enum for reset value.

Pull Request - State: closed - Opened by Fatsie over 5 years ago - 6 comments

#295 - hdl.ast: replace slice.end by slice.stop in ValueKey

Pull Request - State: closed - Opened by psurply over 5 years ago - 3 comments

#294 - Signal: use reset.value if that field exists.

Pull Request - State: closed - Opened by Fatsie over 5 years ago - 2 comments

#293 - (Verilog) nMigen should provide better information about original source code locations

Issue - State: closed - Opened by Maykeye over 5 years ago - 3 comments
Labels: question

#292 - There's no explicit way to convert between signed <-> unsigned values

Issue - State: closed - Opened by Maykeye over 5 years ago - 1 comment
Labels: feature

#291 - Need a way to attach attributes to memories

Issue - State: closed - Opened by JarrettBillingsley over 5 years ago
Labels: feature

#290 - Unclear error message when using an Array as port

Issue - State: closed - Opened by Ravenslofty over 5 years ago
Labels: improvement

#289 - Finding out what resources an nMigen module uses in the output design

Issue - State: closed - Opened by JarrettBillingsley over 5 years ago - 12 comments
Labels: question

#288 - Signal.doc: Mention `range`'s `Shape.cast`able Variant

Issue - State: closed - Opened by peteut over 5 years ago - 1 comment
Labels: improvement

#287 - Document simulator commands

Issue - State: closed - Opened by Ravenslofty over 5 years ago - 1 comment
Labels: duplicate

#286 - Misleading error when trying to use self.comb when inheriting from Module

Issue - State: closed - Opened by asumagic over 5 years ago - 2 comments
Labels: improvement

#285 - Add EnableSignal, useful for making Instances compatible with EnableInserter

Issue - State: open - Opened by Fatsie over 5 years ago - 21 comments
Labels: feature

#284 - if m.If(...): is silently dropped

Issue - State: closed - Opened by Stary2001 over 5 years ago
Labels: improvement

#283 - Record.like() should be a classmethod, not staticmethod.

Issue - State: closed - Opened by kbob over 5 years ago - 3 comments
Labels: question

#282 - Assigning local domain with different name

Issue - State: closed - Opened by Fatsie over 5 years ago
Labels: bug

#281 - Array names revert to "$signal"

Issue - State: closed - Opened by mszep over 5 years ago - 6 comments
Labels: question

#280 - pysim2 doesn't write input signals to VCD

Issue - State: closed - Opened by adamgreig over 5 years ago - 5 comments
Labels: bug, backend:simulator

#279 - hdl.ast: Fix width for unary minus operator on signed argument.

Pull Request - State: closed - Opened by mwkmwkmwk almost 6 years ago - 2 comments

#278 - A little help with defining platform pins?

Issue - State: closed - Opened by RobertBaruch almost 6 years ago - 2 comments
Labels: question

#277 - vendor.intel: silence meaningless warnings

Pull Request - State: closed - Opened by Ravenslofty almost 6 years ago - 7 comments

#276 - Is this a bug in vendor/lattice_ice40?

Issue - State: closed - Opened by RobertBaruch almost 6 years ago - 2 comments

#275 - Remove everything deprecated in nmigen 0.1

Issue - State: closed - Opened by whitequark almost 6 years ago
Labels: improvement

#274 - Signal that is used as both an input and output to an Instance gets assigned to its reset value

Issue - State: closed - Opened by povauboin almost 6 years ago - 1 comment
Labels: bug

#273 - I apparently don't know how to define a ClockDomain

Issue - State: closed - Opened by RobertBaruch almost 6 years ago - 3 comments
Labels: question

#272 - vendor.xilinx_*: Set IOB attribute on cells instead of nets.

Pull Request - State: closed - Opened by jfng almost 6 years ago - 3 comments

#271 - Constant sign-extends incorrectly.

Issue - State: closed - Opened by kbob almost 6 years ago - 6 comments
Labels: bug, backend:RTLIL, backend:verilog

#270 - class Memory: add reset_less parameter that will not initialize memories with 0 value in generated RTL.

Pull Request - State: open - Opened by Fatsie almost 6 years ago - 43 comments
Labels: improvement, backend:simulator

#269 - Platform.add_file(): Allow to add same file with same content multiple times.

Pull Request - State: closed - Opened by Fatsie almost 6 years ago - 2 comments

#263 - On Xilinx platforms, IOB should be set on the cell, not the net

Issue - State: closed - Opened by whitequark almost 6 years ago
Labels: improvement, toolchain:ise, toolchain:vivado

#262 - pure simulation signals should be supported

Issue - State: closed - Opened by sbourdeauducq almost 6 years ago
Labels: improvement, backend:simulator

#254 - Find solution to translate values to strings for Symbiyosys vcd files

Issue - State: open - Opened by RobertBaruch almost 6 years ago - 19 comments
Labels: improvement, upstream

#242 - bitarray dependency is unfortunate

Issue - State: closed - Opened by emilazy almost 6 years ago - 22 comments
Labels: improvement, backend:simulator

#231 - Audit all compat interfaces for breaking changes in argument parsing

Issue - State: closed - Opened by whitequark almost 6 years ago - 3 comments
Labels: improvement

#228 - Reconsider simulator interface

Issue - State: open - Opened by whitequark almost 6 years ago - 42 comments
Labels: improvement, backend:simulator

#215 - pysim treats `x == 1` and `x == -1` for 1-bit signal `x` differently

Issue - State: closed - Opened by whitequark almost 6 years ago
Labels: bug, backend:simulator

#213 - flow graph analysis and automation

Issue - State: open - Opened by jordens almost 6 years ago - 13 comments
Labels: feature

#206 - Enhancing the FSM sub-language

Issue - State: open - Opened by whitequark almost 6 years ago - 12 comments
Labels: improvement

#190 - platform output bus bits in separate modules causes AssertionError

Issue - State: closed - Opened by dlharmon about 6 years ago - 7 comments
Labels: bug

#161 - pysim should have a way to reset user/sync signals

Issue - State: closed - Opened by whitequark about 6 years ago
Labels: feature, backend:simulator

#160 - pysim is very slow

Issue - State: closed - Opened by whitequark about 6 years ago - 4 comments
Labels: improvement, backend:simulator

#108 - Simulations for code that uses Platform

Issue - State: closed - Opened by zignig about 6 years ago - 14 comments
Labels: feature, backend:simulator

#100 - nmigen.compat Case.makedefault() broken

Issue - State: closed - Opened by sbourdeauducq about 6 years ago - 3 comments
Labels: bug

#99 - vendor.xilinx_7series: implement DDR I/O buffers.

Pull Request - State: closed - Opened by jfng about 6 years ago - 1 comment

#98 - Generated Verilog should be more readable

Issue - State: open - Opened by whitequark about 6 years ago - 5 comments
Labels: improvement, upstream, backend:verilog

#97 - Bikeshed: conventions for CDC primitives

Issue - State: closed - Opened by whitequark about 6 years ago - 4 comments
Labels: question

GitHub / m-labs/nmigen issues and pull requests