Ecosyste.ms: Issues

An open API service for providing issue and pull request metadata for open source projects.

GitHub / m-labs/misoc issues and pull requests

#159 - Remove L2 cache synthesis workaround for vivado

Pull Request - State: closed - Opened by occheung 7 days ago

#158 - L2 cache: Reduce grain fine-ness in Vivado synthesis

Pull Request - State: closed - Opened by occheung 9 days ago - 1 comment

#157 - Workaround hold violation by reimplement clock divider in ICAP

Pull Request - State: closed - Opened by occheung 14 days ago

#156 - IBUF_GT: constrain CMT load placement

Pull Request - State: closed - Opened by occheung 17 days ago

#154 - Support larger cache line size for L2 cache

Pull Request - State: closed - Opened by occheung 30 days ago

#151 - Implement Wishbone Burst Support for Memory Controller

Pull Request - State: open - Opened by occheung 3 months ago - 3 comments

#150 - Streaming FIFO: Signals Read/Write Availability using Watermarks

Pull Request - State: open - Opened by occheung 3 months ago - 1 comment

#123 - VexRiscv: Enable Physical Memory Protection (PMP)

Pull Request - State: closed - Opened by occheung over 3 years ago

#100 - Wrong version in `setup.py`

Issue - State: closed - Opened by FFY00 almost 5 years ago

#100 - Wrong version in `setup.py`

Issue - State: closed - Opened by FFY00 almost 5 years ago

#99 - cores: replace use of add_sources(), remove use of add_verilog_include_path()

Pull Request - State: closed - Opened by astro about 5 years ago

#99 - cores: replace use of add_sources(), remove use of add_verilog_include_path()

Pull Request - State: closed - Opened by astro about 5 years ago

#98 - spi2: add iCE40 differential interface

Pull Request - State: closed - Opened by airwoodix over 5 years ago - 9 comments

#98 - spi2: add iCE40 differential interface

Pull Request - State: closed - Opened by airwoodix over 5 years ago - 9 comments

#97 - soc_core:allocate correct size for ROM.

Pull Request - State: open - Opened by keesj almost 6 years ago

#97 - soc_core:allocate correct size for ROM.

Pull Request - State: open - Opened by keesj almost 6 years ago

#96 - register_rom weirdness

Issue - State: open - Opened by keesj almost 6 years ago - 2 comments

#96 - register_rom weirdness

Issue - State: open - Opened by keesj almost 6 years ago - 2 comments

#95 - CSRStorage with write_from_dev=True seems broken in simulation

Issue - State: open - Opened by mithro about 6 years ago - 3 comments

#95 - CSRStorage with write_from_dev=True seems broken in simulation

Issue - State: open - Opened by mithro about 6 years ago - 3 comments

#94 - Use wrap_ts function to wrap signals of core that need tristate output.

Pull Request - State: closed - Opened by Fatsie about 6 years ago - 1 comment

#94 - Use wrap_ts function to wrap signals of core that need tristate output.

Pull Request - State: closed - Opened by Fatsie about 6 years ago - 1 comment

#93 - Wanted to Build a small SoC

Issue - State: closed - Opened by bhatmahadev6 over 6 years ago - 1 comment

#93 - Wanted to Build a small SoC

Issue - State: closed - Opened by bhatmahadev6 over 6 years ago - 1 comment

#92 - fix or remove Ultrascale SDRAM init

Issue - State: closed - Opened by sbourdeauducq over 6 years ago - 4 comments

#92 - fix or remove Ultrascale SDRAM init

Issue - State: closed - Opened by sbourdeauducq over 6 years ago - 4 comments

#91 - software not rebuilt after gateware change

Issue - State: open - Opened by danielkucera over 6 years ago

#91 - software not rebuilt after gateware change

Issue - State: open - Opened by danielkucera over 6 years ago

#90 - added support for qm_xc6slx16_sdram board

Pull Request - State: closed - Opened by danielkucera over 6 years ago

#90 - added support for qm_xc6slx16_sdram board

Pull Request - State: closed - Opened by danielkucera over 6 years ago

#89 - bios: added debug info about flashboot source

Pull Request - State: closed - Opened by danielkucera over 6 years ago - 9 comments

#89 - bios: added debug info about flashboot source

Pull Request - State: closed - Opened by danielkucera over 6 years ago - 9 comments

#88 - added spi 1-bit mode, code from litex

Pull Request - State: open - Opened by danielkucera over 6 years ago - 6 comments

#88 - added spi 1-bit mode, code from litex

Pull Request - State: open - Opened by danielkucera over 6 years ago - 6 comments

#87 - Standard 1 bit SPI mode for spi_flash not available?

Issue - State: open - Opened by danielkucera over 6 years ago - 2 comments

#87 - Standard 1 bit SPI mode for spi_flash not available?

Issue - State: open - Opened by danielkucera over 6 years ago - 2 comments

#86 - Added missing default argument

Pull Request - State: closed - Opened by kaolpr over 6 years ago - 3 comments

#86 - Added missing default argument

Pull Request - State: closed - Opened by kaolpr over 6 years ago - 3 comments

#85 - Support for AFC 3v1

Pull Request - State: closed - Opened by kaolpr over 6 years ago - 2 comments

#85 - Support for AFC 3v1

Pull Request - State: closed - Opened by kaolpr over 6 years ago - 2 comments

#84 - Fix repetition in README.

Pull Request - State: closed - Opened by mgielda over 6 years ago - 1 comment

#84 - Fix repetition in README.

Pull Request - State: closed - Opened by mgielda over 6 years ago - 1 comment

#83 - Binutils compilation

Issue - State: open - Opened by danielkucera over 6 years ago

#83 - Binutils compilation

Issue - State: open - Opened by danielkucera over 6 years ago

#82 - Obtain gateware toolchain path from environment variable

Pull Request - State: closed - Opened by kaolpr over 6 years ago - 5 comments

#82 - Obtain gateware toolchain path from environment variable

Pull Request - State: closed - Opened by kaolpr over 6 years ago - 5 comments

#81 - correctly use result of Record.connect in Converter

Pull Request - State: closed - Opened by tpwrules over 6 years ago - 1 comment

#81 - correctly use result of Record.connect in Converter

Pull Request - State: closed - Opened by tpwrules over 6 years ago - 1 comment

#80 - Record.connect return value not used

Issue - State: closed - Opened by tpwrules over 6 years ago - 3 comments
Labels: bug

#80 - Record.connect return value not used

Issue - State: closed - Opened by tpwrules over 6 years ago - 3 comments
Labels: bug

#79 - Sayma: remove unnecessary LOCs

Pull Request - State: closed - Opened by hartytp over 6 years ago - 5 comments

#79 - Sayma: remove unnecessary LOCs

Pull Request - State: closed - Opened by hartytp over 6 years ago - 5 comments

#78 - VexRiscv integration

Pull Request - State: closed - Opened by Dolu1990 almost 7 years ago - 13 comments

#78 - VexRiscv integration

Pull Request - State: closed - Opened by Dolu1990 almost 7 years ago - 13 comments

#77 - make SPI2 work for busses with no MOSI (e.g. ADCs like Sampler)

Pull Request - State: closed - Opened by hartytp almost 7 years ago - 1 comment

#77 - make SPI2 work for busses with no MOSI (e.g. ADCs like Sampler)

Pull Request - State: closed - Opened by hartytp almost 7 years ago - 1 comment

#75 - DDR3-related error in Vivado timing report for Ultrascale

Issue - State: closed - Opened by sbourdeauducq about 7 years ago - 1 comment

#75 - DDR3-related error in Vivado timing report for Ultrascale

Issue - State: closed - Opened by sbourdeauducq about 7 years ago - 1 comment

#74 - kasli/spi_flash: investigate and implement quad i/o read

Issue - State: open - Opened by jordens about 7 years ago
Labels: improvement

#74 - kasli/spi_flash: investigate and implement quad i/o read

Issue - State: open - Opened by jordens about 7 years ago
Labels: improvement

#73 - clean up memory regions, names, offsets

Issue - State: open - Opened by jordens about 7 years ago
Labels: improvement

#73 - clean up memory regions, names, offsets

Issue - State: open - Opened by jordens about 7 years ago
Labels: improvement

#72 - liteeth: remove MII clock output

Issue - State: open - Opened by sbourdeauducq about 7 years ago

#72 - liteeth: remove MII clock output

Issue - State: open - Opened by sbourdeauducq about 7 years ago

#71 - liteeth: rename dv to rx_dv

Issue - State: closed - Opened by sbourdeauducq about 7 years ago

#71 - liteeth: rename dv to rx_dv

Issue - State: closed - Opened by sbourdeauducq about 7 years ago

#70 - liteeth: remove dw parameterization

Issue - State: closed - Opened by sbourdeauducq about 7 years ago - 2 comments

#70 - liteeth: remove dw parameterization

Issue - State: closed - Opened by sbourdeauducq about 7 years ago - 2 comments

#69 - fix liteeth error counter atomicity problem

Issue - State: open - Opened by sbourdeauducq about 7 years ago - 2 comments

#69 - fix liteeth error counter atomicity problem

Issue - State: open - Opened by sbourdeauducq about 7 years ago - 2 comments

#68 - replace liteeth _preamble_crc CSR with constant

Issue - State: closed - Opened by sbourdeauducq about 7 years ago

#68 - replace liteeth _preamble_crc CSR with constant

Issue - State: closed - Opened by sbourdeauducq about 7 years ago

#67 - remove gap checker from liteeth

Issue - State: closed - Opened by sbourdeauducq about 7 years ago - 1 comment

#67 - remove gap checker from liteeth

Issue - State: closed - Opened by sbourdeauducq about 7 years ago - 1 comment

#66 - flterm: memory leak

Issue - State: closed - Opened by jbqubit about 7 years ago - 7 comments
Labels: bug

#66 - flterm: memory leak

Issue - State: closed - Opened by jbqubit about 7 years ago - 7 comments
Labels: bug

#65 - SPI clock glitches on CS transitions

Issue - State: closed - Opened by jordens about 7 years ago
Labels: bug

#65 - SPI clock glitches on CS transitions

Issue - State: closed - Opened by jordens about 7 years ago
Labels: bug

#64 - liteeth should be tolerant to truncated or garbled preambles

Issue - State: closed - Opened by jordens about 7 years ago - 1 comment
Labels: bug

#64 - liteeth should be tolerant to truncated or garbled preambles

Issue - State: closed - Opened by jordens about 7 years ago - 1 comment
Labels: bug

#63 - DDR3 broken on some Sayma boards

Issue - State: closed - Opened by sbourdeauducq about 7 years ago - 5 comments

#63 - DDR3 broken on some Sayma boards

Issue - State: closed - Opened by sbourdeauducq about 7 years ago - 5 comments

#62 - check that liteeth MAC observes minimum interframe gap

Issue - State: closed - Opened by jordens about 7 years ago - 1 comment

#62 - check that liteeth MAC observes minimum interframe gap

Issue - State: closed - Opened by jordens about 7 years ago - 1 comment

#61 - Compiling gcc-7.2.0

Issue - State: closed - Opened by FelixVi about 7 years ago - 5 comments

#61 - Compiling gcc-7.2.0

Issue - State: closed - Opened by FelixVi about 7 years ago - 5 comments

#60 - Papilio pro default rom size is too small

Issue - State: closed - Opened by FelixVi about 7 years ago - 8 comments

#60 - Papilio pro default rom size is too small

Issue - State: closed - Opened by FelixVi about 7 years ago - 8 comments

#59 - Paths broken when using Cygwin and Xilinx tools in Windows

Issue - State: closed - Opened by FelixVi about 7 years ago - 1 comment

#59 - Paths broken when using Cygwin and Xilinx tools in Windows

Issue - State: closed - Opened by FelixVi about 7 years ago - 1 comment

#58 - cross check SPI core w.r.t. Vivado changes

Issue - State: open - Opened by jordens about 7 years ago

#58 - cross check SPI core w.r.t. Vivado changes

Issue - State: open - Opened by jordens about 7 years ago

#57 - merge a7ddrphy and k7ddrphy

Issue - State: open - Opened by sbourdeauducq over 7 years ago - 5 comments

#57 - merge a7ddrphy and k7ddrphy

Issue - State: open - Opened by sbourdeauducq over 7 years ago - 5 comments

#56 - Bunch of small fixes

Pull Request - State: open - Opened by mithro over 7 years ago

#56 - Bunch of small fixes

Pull Request - State: open - Opened by mithro over 7 years ago

#55 - RGMII on Sayma broken

Issue - State: closed - Opened by jordens over 7 years ago - 8 comments
Labels: feature