m-labs/migen issues and pull requests

#201 - generic_platform: add copy_sources(), remove verilog_include_paths

Pull Request - State: closed - Opened by astro about 5 years ago - 14 comments

#200 - xilinx/vivado: emit sorted sources for top.tcl

Pull Request - State: closed - Opened by astro about 5 years ago

#199 - SyntaxWarning in migen\migen\fhdl\visit.py

Issue - State: closed - Opened by mithro about 5 years ago

#198 - Add integer attributes

Pull Request - State: closed - Opened by DurandA about 5 years ago - 2 comments

#195 - Added most of Basemod AFE pins for Sayma AMC and RTM

Pull Request - State: closed - Opened by marmeladapk about 5 years ago - 1 comment

#189 - Add inline attributes to instance

Pull Request - State: closed - Opened by DurandA over 5 years ago - 15 comments

#179 - Conda installation fails

Issue - State: closed - Opened by chipmuenk over 5 years ago - 10 comments
Labels: question

#121 - Not able to simulate

Issue - State: closed - Opened by bhatmahadev6 over 6 years ago - 10 comments

#107 - dual-port, writable, READ_FIRST, memory pattern not recognized

Issue - State: open - Opened by jordens over 6 years ago - 1 comment
Labels: bug

#100 - build: quartus: prevent conversion to RBF when no SOF is generated

Pull Request - State: closed - Opened by psurply about 7 years ago

#99 - make post-synthesis results compatible with Vivado GUI

Issue - State: open - Opened by sbourdeauducq about 7 years ago - 1 comment
Labels: feature

#98 - fhdl/tracer: Add guard code to support Python 3.6. Closes #62.

Pull Request - State: closed - Opened by cr1901 about 7 years ago - 1 comment

#97 - fhdl/tracer: Support Python 3.5 `CALL_FUNCTION{_VAR}_KW`. Closes #94

Pull Request - State: closed - Opened by cr1901 about 7 years ago

#96 - Add DE0-Nano-SoC (aka Atlas-SoC) platform

Pull Request - State: closed - Opened by adamgreig about 7 years ago - 1 comment

#95 - Add MyStorm BlackIce I and II platforms

Pull Request - State: closed - Opened by adamgreig about 7 years ago - 10 comments

#94 - Support all function call opcodes in Python 3.5 in tracer.py

Issue - State: closed - Opened by cr1901 about 7 years ago - 4 comments

#93 - update comment for memory fix

Pull Request - State: closed - Opened by nakengelhardt about 7 years ago

#92 - fhdl/verilog: Don't emit constants larger than bit width for signed constants

Pull Request - State: closed - Opened by adamgreig about 7 years ago - 2 comments

#91 - make memory simulation behavior for read ports same as emitted verilog

Pull Request - State: closed - Opened by nakengelhardt about 7 years ago - 5 comments

#90 - fix data output changing while not reading when fifo is full in non-fwft mode

Pull Request - State: closed - Opened by nakengelhardt about 7 years ago - 1 comment

#89 - build/platforms/de0nano: Fix incorrect sw1 pin assignment: T9->T8

Pull Request - State: closed - Opened by adamgreig about 7 years ago - 1 comment

#88 - xilinx/ise: Add Cygwin path to Windows conversion in xst files.

Pull Request - State: closed - Opened by cr1901 about 7 years ago - 11 comments

#87 - Add Mercury Baseboard support

Pull Request - State: closed - Opened by cr1901 about 7 years ago

#86 - Add Platform-specific tests

Pull Request - State: closed - Opened by cr1901 about 7 years ago

#85 - Add TinyFPGA B Platform

Pull Request - State: closed - Opened by cr1901 about 7 years ago

#84 - Icestorm Backend Improvements

Pull Request - State: closed - Opened by cr1901 about 7 years ago - 2 comments

#83 - Driving a ClockDomain is broken in sim

Issue - State: closed - Opened by shuffle2 about 7 years ago - 3 comments
Labels: question

#82 - redesign platform resource

Issue - State: open - Opened by jordens about 7 years ago - 3 comments
Labels: feature, improvement

#81 - io_name = io.backtrace[-1][0] IndexError: list index out of range

Issue - State: closed - Opened by redfast00 over 7 years ago - 1 comment
Labels: bug

#80 - tutorial out of date (was: Issue with importing Signal)

Issue - State: open - Opened by sheeets over 7 years ago - 3 comments
Labels: bug

#79 - Output better error message for flash_proxy.

Pull Request - State: open - Opened by mithro over 7 years ago - 2 comments

#78 - Slightly improve the documentation of the FIFO interfaces.

Pull Request - State: closed - Opened by mithro over 7 years ago - 2 comments

#77 - document platform, toolchain API and build process hooks

Issue - State: open - Opened by jordens over 7 years ago
Labels: improvement

#76 - document constraints API

Issue - State: open - Opened by jordens over 7 years ago
Labels: improvement

#75 - sim/verilog mismatch: mux

Issue - State: open - Opened by jordens over 7 years ago
Labels: bug, fixed-in-nmigen

#74 - Add spi sd card entry

Pull Request - State: closed - Opened by mntng over 7 years ago - 2 comments

#73 - AsyncFIFO reset

Issue - State: open - Opened by jordens over 7 years ago - 2 comments
Labels: improvement, fixed-in-nmigen

#72 - cdc: make pipelined registers reset_less

Pull Request - State: closed - Opened by jordens over 7 years ago - 12 comments

#71 - Add 'depth' attribute to _FIFOInterface

Pull Request - State: closed - Opened by lukaslaobeyer over 7 years ago

#70 - export as hierarchy (verilog modules)

Issue - State: open - Opened by jordens over 7 years ago - 6 comments
Labels: feature, fixed-in-nmigen

#69 - construct and use sensitivity graph to speed up sim and find comb loops

Issue - State: open - Opened by jordens over 7 years ago - 2 comments
Labels: improvement, fixed-in-nmigen

#68 - add nexsys3 support

Pull Request - State: closed - Opened by anuejn over 7 years ago - 2 comments

#67 - Implement contains() method for _ClockDomainList class

Pull Request - State: closed - Opened by rohitk-singh almost 8 years ago

#66 - Migen generates redundant clock domains when using run_simulation()

Issue - State: closed - Opened by rohitk-singh almost 8 years ago - 2 comments

#65 - doc: Enable canonical_url only on readthedocs.

Pull Request - State: closed - Opened by mithro almost 8 years ago

#64 - Small docs improvements

Pull Request - State: closed - Opened by mithro almost 8 years ago

#63 - consider removing the depth parameter of ElasticBuffer

Issue - State: open - Opened by sbourdeauducq about 8 years ago - 1 comment
Labels: question

#62 - Python 3.6 support

Issue - State: closed - Opened by sbourdeauducq about 8 years ago - 12 comments

#61 - support asymmetric dual-port memories

Issue - State: open - Opened by sbourdeauducq about 8 years ago - 1 comment
Labels: feature

#60 - Added clock argument to specify arbitrary clock network

Pull Request - State: closed - Opened by hutch31 about 8 years ago - 2 comments

#59 - sensitivity list and negative clock edge

Issue - State: closed - Opened by raspberrypisig about 8 years ago - 2 comments

#58 - constrain CDCs with max_delay [vivado]

Issue - State: open - Opened by jordens about 8 years ago - 1 comment
Labels: improvement, fixed-in-nmigen

#57 - add platform file for DE0-CV

Pull Request - State: closed - Opened by flashcactus about 8 years ago

#56 - Assignment to slices,

Issue - State: closed - Opened by benreynwar about 8 years ago - 8 comments

#55 - support reset-less Signals (closes #54)

Pull Request - State: closed - Opened by jordens about 8 years ago - 3 comments

#54 - support reset-less Signals

Issue - State: closed - Opened by jordens about 8 years ago - 4 comments

#53 - FullMemoryWE and SplitMemory break direct access to memory in simulation

Issue - State: open - Opened by jordens about 8 years ago - 1 comment
Labels: improvement, fixed-in-nmigen

#52 - Set the width and signedness of the reset value.

Pull Request - State: closed - Opened by benreynwar about 8 years ago - 4 comments

#51 - Add an explanation of the dummy_s into the generated verilog.

Pull Request - State: closed - Opened by benreynwar about 8 years ago - 7 comments

#50 - mixing comb and sync assignments of a signal's bits doesn't work

Issue - State: closed - Opened by jordens about 8 years ago - 7 comments
Labels: question

#49 - FullMemoryWE breaks simulation

Issue - State: closed - Opened by jordens about 8 years ago

#48 - AsyncResetSynchronizer needs more timing constraints

Issue - State: closed - Opened by jordens about 8 years ago - 1 comment

#47 - mkdir_noerror() don't create multideph directories

Issue - State: closed - Opened by rogeriomm over 8 years ago - 2 comments

#46 - Mux not supported in value_bits_sign()

Issue - State: closed - Opened by jordens almost 9 years ago

#45 - namer issue with signed signals

Issue - State: closed - Opened by jordens almost 9 years ago - 1 comment

#44 - unary minus not handled in value_bits_sign()

Issue - State: closed - Opened by jordens almost 9 years ago

#43 - Can't use TIG on same TNM as period constraints in ISE

Issue - State: closed - Opened by mithro almost 9 years ago - 1 comment

#42 - stabilize and de-randomize verilog output

Issue - State: closed - Opened by jordens almost 9 years ago - 6 comments

#41 - Records with 0 fields generate invalid verilog

Issue - State: open - Opened by nakengelhardt almost 9 years ago - 4 comments
Labels: bug, fixed-in-nmigen

#40 - Consistent I/O names on top level

Issue - State: closed - Opened by enjoy-digital almost 9 years ago - 3 comments

#39 - When ISE/Vivado are unavailable, show a decent error message

Issue - State: closed - Opened by whitequark almost 9 years ago

#38 - compiling a project giving error

Issue - State: closed - Opened by Goddard almost 9 years ago - 1 comment

#37 - Exception now has helpful string.

Pull Request - State: closed - Opened by mithro about 9 years ago

#36 - Simulator issue

Issue - State: closed - Opened by jordens about 9 years ago - 2 comments

#35 - Formatting in README is broken

Issue - State: closed - Opened by whitequark about 9 years ago

#34 - Simulating MultiReg with new simulator

Issue - State: closed - Opened by enjoy-digital about 9 years ago

#33 - incorrect Cat element width in Verilog export

Issue - State: open - Opened by sbourdeauducq over 9 years ago
Labels: bug, fixed-in-nmigen

#32 - upload migen package on pypi

Issue - State: closed - Opened by fallen over 9 years ago - 1 comment

#31 - fixed bug in value_bits_sign of mul operatiors

Pull Request - State: closed - Opened by burnpanck over 9 years ago - 4 comments

#30 - CSR should have read and write swapped to master perspective

Issue - State: closed - Opened by jordens over 9 years ago - 1 comment

#29 - Migen Namer main Decoration

Issue - State: open - Opened by cr1901 over 9 years ago - 4 comments
Labels: improvement, fixed-in-nmigen

#28 - Migen Simulation ClockDomainsRenamer renaming error

Issue - State: closed - Opened by cr1901 over 9 years ago - 1 comment

#27 - support arrays in NextValue

Issue - State: closed - Opened by sbourdeauducq over 9 years ago

#26 - Dock Area crash upon artiq_gui restart

Issue - State: closed - Opened by tingrei86 over 9 years ago

#25 - travis: do not indicate build success when package upload fails

Issue - State: closed - Opened by sbourdeauducq over 9 years ago - 1 comment

#24 - add_platform_command should support ClockSignal() and ResetSignal()

Issue - State: closed - Opened by sbourdeauducq over 9 years ago

#23 - Missing documentation for migen.genlib modules

Issue - State: open - Opened by mithro over 9 years ago - 1 comment
Labels: improvement

#22 - Warning from examples/sim/memory.py

Issue - State: closed - Opened by mithro over 9 years ago - 1 comment

#21 - Minor improvements to wording

Pull Request - State: closed - Opened by psmears over 9 years ago - 1 comment

#20 - Cat(..)[slice] on LHS needs a proxy

Issue - State: open - Opened by cr1901 over 9 years ago - 4 comments
Labels: bug, fixed-in-nmigen

#19 - Added simple example of Case statement, and updated documentation

Pull Request - State: closed - Opened by hutch31 over 9 years ago

#18 - iverilog vpi on windows: (i + nchunks == l) assertion fails

Issue - State: closed - Opened by enjoy-digital over 9 years ago - 1 comment
Labels: bug

#17 - migen travis config should push development versions to PyPi

Issue - State: open - Opened by mithro almost 10 years ago - 1 comment
Labels: improvement

#16 - mibuild: Support FPGALink / NeroJTAG as a programmer (and maybe computer interface?)

Issue - State: closed - Opened by mithro almost 10 years ago - 2 comments
Labels: feature, question

#15 - minispartan6+ board comes in xc6slx9 and xc6slx25 versions

Issue - State: closed - Opened by mithro almost 10 years ago - 1 comment
Labels: feature, question

#14 - Fix shadowing of global declarations in vpi/ipc.c

Issue - State: closed - Opened by mithro almost 10 years ago - 1 comment
Labels: improvement

#13 - migen README still doesn't link to the readthedocs.org documentation - is there something wrong with it?

Issue - State: closed - Opened by mithro almost 10 years ago - 5 comments
Labels: improvement, question

#12 - migen version of "unknown" in setup.py is invalid

Issue - State: closed - Opened by mithro almost 10 years ago - 3 comments
Labels: improvement

#11 - vpi module install to /usr/lib/ivl but iverilog uses /usr/lib/x86_64-linux-gnu/ivl

Issue - State: closed - Opened by mithro almost 10 years ago
Labels: improvement

#10 - migen CI support

Issue - State: closed - Opened by mithro almost 10 years ago - 2 comments
Labels: feature

GitHub / m-labs/migen issues and pull requests