Ecosyste.ms: Issues

An open API service for providing issue and pull request metadata for open source projects.

GitHub / m-labs/migen issues and pull requests

#298 - Add support for more call opcodes.

Pull Request - State: closed - Opened by jasonbridges about 2 months ago - 4 comments

#297 - Support for python 3.13

Issue - State: open - Opened by jasonbridges about 2 months ago

#295 - Fix Signal initialization when max=1

Pull Request - State: closed - Opened by andelf 3 months ago - 4 comments

#294 - Implement almost_full and almost_empty for Synchronous FIFOs

Pull Request - State: closed - Opened by occheung 3 months ago

#293 - Ebaz4205 update2

Pull Request - State: closed - Opened by newell 4 months ago - 3 comments

#292 - fhdl/structure: add check for equality for _Slice

Pull Request - State: open - Opened by maass-hamburg 4 months ago - 5 comments

#291 - zc706: AJ7 net name fix

Pull Request - State: closed - Opened by MorganTL 5 months ago - 2 comments

#290 - Refactor PS portion to migen-axi

Pull Request - State: closed - Opened by newell 6 months ago

#288 - Python 3.12 namer issue

Issue - State: closed - Opened by sbourdeauducq 7 months ago

#287 - EBAZ4205 update1

Pull Request - State: closed - Opened by newell 7 months ago

#286 - Add EBAZ4205 board to platforms.

Pull Request - State: closed - Opened by newell 7 months ago

#285 - FSM.ongoing is broken or...

Issue - State: closed - Opened by shareefj 7 months ago - 2 comments

#284 - Updated EEM FMC Carrier platform for v1.1

Pull Request - State: closed - Opened by kaolpr 9 months ago

#283 - migen/fhdl/tracer.py: update get_var_name() from amaranth

Pull Request - State: open - Opened by maribu about 1 year ago

#282 - pyproject.toml: add build backend

Pull Request - State: closed - Opened by gsomlo about 1 year ago

#281 - feature: add Module.print_hierarchy

Pull Request - State: open - Opened by shareefj about 1 year ago - 6 comments

#280 - kasli_soc: add user_led2

Pull Request - State: closed - Opened by SimonRenblad about 1 year ago - 4 comments

#279 - zc706: correct the speed grade in the fpga part number

Pull Request - State: closed - Opened by linuswck over 1 year ago

#278 - efc: add support for custom platform name

Pull Request - State: closed - Opened by linuswck over 1 year ago - 1 comment

#277 - Add OOB reset user attributes for ARTIQ

Pull Request - State: closed - Opened by occheung over 1 year ago

#276 - Replace setup.py with pyproject.toml

Pull Request - State: closed - Opened by davidbrochart over 1 year ago

#275 - Subvector of Cat() incorrect assignment

Issue - State: closed - Opened by noiuynoise over 1 year ago - 1 comment

#274 - `else` branch elided in generated Verilog

Issue - State: open - Opened by McSherry over 1 year ago - 3 comments

#273 - Fix EFC pinout - HB09_N

Pull Request - State: closed - Opened by marmeladapk about 2 years ago

#272 - EFC platform - swap FMC CLK BIDIR polarity

Pull Request - State: closed - Opened by marmeladapk about 2 years ago

#271 - Added support for EEM FMC Carrier

Pull Request - State: closed - Opened by marmeladapk about 2 years ago

#270 - build/tools: language_by_filename, add SystemVerilog extensions to Verilog

Pull Request - State: closed - Opened by JammyL about 2 years ago

#269 - Better FMC support

Issue - State: open - Opened by kaolpr about 2 years ago - 1 comment

#268 - add red pitaya 7020 variant

Pull Request - State: closed - Opened by TopQuark12 about 2 years ago - 2 comments

#267 - [Sim] Error with fsm delayed_enter method

Issue - State: open - Opened by kamejoko80 over 2 years ago

#266 - Invalid synthesis output for TSTriple width > 1 (Vivado)

Issue - State: closed - Opened by kaolpr over 2 years ago - 1 comment

#265 - Problem with an instance

Issue - State: closed - Opened by ramalmar over 2 years ago - 1 comment

#264 - Added support for Digilent Genesys 2 platform.

Pull Request - State: closed - Opened by kaolpr over 2 years ago

#263 - Added post synthesis commands to Xilinx Vivado toolchain.

Pull Request - State: closed - Opened by kaolpr over 2 years ago

#262 - Fix ECP5 BRAM packing

Pull Request - State: open - Opened by madscientist159 over 2 years ago - 2 comments

#261 - fhdl/tracer: update to support python 3.11

Pull Request - State: closed - Opened by gsomlo over 2 years ago - 3 comments

#260 - zc706: la26_p pin fix

Pull Request - State: closed - Opened by Spaqin almost 3 years ago

#259 - tests fail when building with Python 3.11

Issue - State: closed - Opened by gsomlo almost 3 years ago - 4 comments

#257 - Insert a `define in the top scope

Issue - State: closed - Opened by smosanu almost 3 years ago - 1 comment

#256 - Incorrect simulation of Cat()

Issue - State: open - Opened by enurseitov almost 3 years ago - 3 comments

#255 - Unable to build gateware for Kasli v2.0

Issue - State: closed - Opened by rgresia almost 3 years ago - 1 comment

#254 - sayma_amc2: fix missing FPGA<->CPU SPI pins

Pull Request - State: closed - Opened by HarryMakes about 3 years ago

#253 - vivado: improve timing during opt_design

Pull Request - State: closed - Opened by occheung about 3 years ago

#252 - Instance parameter value needlessly translated to narrowed width causes errors

Issue - State: closed - Opened by smosanu about 3 years ago - 5 comments

#251 - zc706: added pmod1 and xadc connector

Pull Request - State: closed - Opened by Spaqin over 3 years ago

#250 - zc706: add user_sma_mgt

Pull Request - State: closed - Opened by Spaqin over 3 years ago

#249 - kasli_soc: cdr_clk: replaced lvds_18 with lvds_25

Pull Request - State: closed - Opened by Spaqin over 3 years ago

#248 - data change issue inside FSM state

Issue - State: closed - Opened by jimmymagemtek over 3 years ago

#247 - Signal Names of FSM

Issue - State: open - Opened by navaneeth-cirel over 3 years ago

#246 - TSTriple() usage

Issue - State: open - Opened by jimmymagemtek over 3 years ago

#245 - ClockDomain "helper" used for I2C master

Issue - State: closed - Opened by jimmymagemtek over 3 years ago

#244 - How to create a ClockDomain for I2C ?

Issue - State: closed - Opened by jimmymagemtek over 3 years ago - 1 comment

#243 - Kc705/zc706 SFP signals changes

Pull Request - State: closed - Opened by Spaqin over 3 years ago

#242 - zc706 platform: add SFP and Si5324 signals

Pull Request - State: closed - Opened by Spaqin over 3 years ago

#241 - question

Issue - State: closed - Opened by Saqlinahamad over 3 years ago

#240 - FSM() always reset the fields being modified in the beginning of the loop

Issue - State: closed - Opened by jimmymagemtek over 3 years ago - 2 comments

#239 - how to put more than one statement in each case value ?

Issue - State: closed - Opened by jimmymagemtek over 3 years ago

#238 - Cycle accurate simulation

Issue - State: open - Opened by navaneeth-cirel over 3 years ago - 2 comments

#237 - specials: Update mem.init files to match expectation of ecpbram

Pull Request - State: closed - Opened by meklort almost 4 years ago - 4 comments

#236 - kasli_soc: fix pin eem4.d1_p

Pull Request - State: closed - Opened by astro almost 4 years ago

#235 - review kasli_soc pinout

Issue - State: closed - Opened by sbourdeauducq almost 4 years ago - 4 comments

#234 - kasli_soc: fix sma_clkin and eem pins

Pull Request - State: closed - Opened by astro about 4 years ago

#233 - How to convert migen source code into to Verilog?

Issue - State: closed - Opened by rajhlinux about 4 years ago - 2 comments

#232 - [WIP] coraz7: fix _connectors

Pull Request - State: open - Opened by astro about 4 years ago

#231 - build/xilinx: Add support for newer symbiflow versions

Pull Request - State: closed - Opened by CajuM about 4 years ago

#230 - Added documentation to AsyncResetSynchronizer

Pull Request - State: closed - Opened by Wardstein about 4 years ago - 2 comments

#229 - Added documentation to AsyncResetSynchronizer

Pull Request - State: closed - Opened by Wardstein about 4 years ago

#228 - Migen - Cat() simulation not matching verilog when Cat_object is sliced

Issue - State: open - Opened by scted about 4 years ago - 8 comments

#227 - platforms: add sinara/kasli_soc

Pull Request - State: closed - Opened by astro about 4 years ago - 1 comment

#226 - coraz7: rename to accomodate both hardware models

Pull Request - State: closed - Opened by astro about 4 years ago

#225 - Add module name to vcd

Pull Request - State: closed - Opened by pifry over 4 years ago - 5 comments

#224 - Possibly incorrect VCD file generated

Issue - State: closed - Opened by pifry over 4 years ago - 1 comment

#223 - Add example for a design that runs on a board, e.g. red pitaya

Issue - State: closed - Opened by lneuhaus over 4 years ago - 2 comments

#222 - build/quicklogic: add support for Quicklogic toolchain

Pull Request - State: closed - Opened by kowalewskijan over 4 years ago - 2 comments

#221 - [enh] use Misc() properties in trellis' PCF

Pull Request - State: open - Opened by chmousset over 4 years ago - 1 comment

#220 - fhdl/simplify: sort specials before init-ing new DUID objects

Pull Request - State: closed - Opened by HarryMakes over 4 years ago

#218 - python dependency wheel missing

Issue - State: open - Opened by philipaxer over 4 years ago

#217 - examples/sim: add shift(-right) register examples

Pull Request - State: open - Opened by HarryMakes over 4 years ago - 1 comment

#216 - bitwise invert of unsigned int is negative

Issue - State: closed - Opened by BrettRD over 4 years ago - 4 comments

#215 - SyncFIFO self.writable signal is one cycle delayed

Issue - State: closed - Opened by mtdudek over 4 years ago - 1 comment

#214 - xilinx: add DDRInput for Spartan6

Pull Request - State: closed - Opened by tcrs over 4 years ago

#213 - metlino: add SFP CTL pins

Pull Request - State: closed - Opened by HarryMakes over 4 years ago

#212 - Fix Si5324 reset.

Pull Request - State: closed - Opened by marmeladapk over 4 years ago - 1 comment

#211 - Add initial support for Symbiflow toolchain for xc7

Pull Request - State: closed - Opened by mglb over 4 years ago - 1 comment

#210 - zc706: redo FMC connectors

Pull Request - State: closed - Opened by astro over 4 years ago - 1 comment

#209 - zc706: add FMC HPC connector HA pins

Pull Request - State: closed - Opened by astro over 4 years ago

#208 - zc706: add FMC connectors

Pull Request - State: closed - Opened by astro over 4 years ago - 1 comment

#207 - Problem with copy_sources(self, build_dir, subdir="imports")

Issue - State: open - Opened by andres-emb almost 5 years ago - 7 comments

#206 - platforms: add zc706 + coraz7_07s

Pull Request - State: closed - Opened by astro almost 5 years ago

#205 - migen.fhdl.specials: add per bit oe option to TSTriple

Pull Request - State: open - Opened by TomKeddie almost 5 years ago - 2 comments

#204 - Sayma RTM Basemod 1 amplifier An pin placement fix

Pull Request - State: closed - Opened by kaolpr about 5 years ago

#203 - Fixed Sayma AMC BaseMod1 SPI clock pin location

Pull Request - State: closed - Opened by kaolpr about 5 years ago

#202 - vivado: split build script in two steps

Pull Request - State: closed - Opened by astro about 5 years ago - 2 comments