lowrisc/style-guides issues and pull requests

#77 - Synchronous active-high reset

Pull Request - State: closed - Opened by mgottscho 3 months ago

#76 - Update title and create CHANGELOG.adoc

Pull Request - State: closed - Opened by mgottscho 3 months ago - 1 comment

#75 - Enum typedefs use _t instead of _e

Pull Request - State: closed - Opened by mgottscho 3 months ago

#74 - Remove `_i` and `_o` naming convention

Pull Request - State: closed - Opened by mgottscho 3 months ago - 2 comments

#73 - Why is SV interface usage discouraged ?

Issue - State: closed - Opened by arnonsha about 1 year ago - 1 comment

#72 - Fix typo in code example

Pull Request - State: closed - Opened by rswarbrick about 1 year ago

#71 - typo in the Suffixes

Issue - State: closed - Opened by OlgaEsula about 1 year ago - 1 comment

#70 - FSM must be implement with two process blocks

Issue - State: closed - Opened by danieldanino17 about 1 year ago - 1 comment
Labels: question

#69 - Fix inconsistent use of simulation/synthesis mismatch

Pull Request - State: closed - Opened by rfdonnelly about 1 year ago - 1 comment

#68 - Inconsistent use of "simulation-synthesis mismatch"

Issue - State: closed - Opened by rfdonnelly about 1 year ago - 1 comment

#67 - Continuous assignment from argumentless functions

Issue - State: open - Opened by sifferman over 1 year ago - 2 comments

#66 - Functions should avoid non-local references

Pull Request - State: closed - Opened by sifferman over 1 year ago - 11 comments

#65 - Plagarism of the Google Verilog Style Guide

Issue - State: closed - Opened by jonmayer about 2 years ago - 2 comments

#64 - Stance on wand / wor?

Issue - State: closed - Opened by johnMamish over 2 years ago - 1 comment
Labels: question

#63 - Parameter naming convention inconsistencies

Issue - State: open - Opened by colluca over 2 years ago

#62 - [SVA] Provide guidance on SVAs

Pull Request - State: closed - Opened by sriyerg over 2 years ago - 1 comment

#61 - [dv] add `Wait And Non-Forever Loop` guidance

Pull Request - State: closed - Opened by weicaiyang over 2 years ago

#60 - add a reference to sv-tests

Pull Request - State: closed - Opened by josuah over 2 years ago - 2 comments

#59 - fix two guideline deviations in the examples

Pull Request - State: closed - Opened by josuah over 2 years ago

#58 - Add guidelines for chip-level test forcing and probing

Pull Request - State: closed - Opened by weicaiyang over 2 years ago

#57 - Discourage the use of hierarchical references in synthesiable RTL code

Pull Request - State: closed - Opened by vogelpi about 3 years ago - 1 comment

#56 - Linting file for spyglass

Issue - State: open - Opened by rahulraveendran15-coder over 3 years ago - 5 comments
Labels: question

#55 - Guidance on whether to add space between SV keyword 'wait' and parenthesis

Issue - State: closed - Opened by sriyerg over 3 years ago - 3 comments

#54 - Exemptions on 'spaces around keywords' rule

Pull Request - State: closed - Opened by sriyerg over 3 years ago - 1 comment

#53 - [sv] How to format module instantiations that fit in a single line?

Issue - State: open - Opened by imphil over 3 years ago - 5 comments

#52 - Use of SystemVerilog Interfaces

Issue - State: open - Opened by MikeOpenHWGroup over 3 years ago - 12 comments

#51 - Fix example code

Pull Request - State: closed - Opened by imphil almost 4 years ago

#50 - Format module port expressions in tabular style

Pull Request - State: closed - Opened by imphil almost 4 years ago - 6 comments

#49 - Prefer SystemVerilog 2017 instead of 2012

Pull Request - State: closed - Opened by imphil almost 4 years ago - 1 comment

#48 - How to align named ports in module instantiations?

Issue - State: closed - Opened by imphil almost 4 years ago - 17 comments

#47 - [style] Align FSM examples with register naming rule

Pull Request - State: closed - Opened by msfschaffner almost 4 years ago - 1 comment

#46 - DV style guide: mention non-compliant usage of disable

Pull Request - State: closed - Opened by imphil about 4 years ago - 2 comments

#45 - [dv style guide] More macro usage guidelines

Pull Request - State: closed - Opened by sriyerg over 4 years ago - 1 comment

#44 - blocking assignment must be used for a clock divider

Pull Request - State: open - Opened by hirooih over 4 years ago - 9 comments

#43 - Prefer SystemVerilog-2017 instead of 2012

Issue - State: closed - Opened by hirooih over 4 years ago - 6 comments

#42 - Clarification changes

Pull Request - State: closed - Opened by hirooih over 4 years ago - 3 comments

#41 - Scope of this style guide and questions

Issue - State: open - Opened by hirooih over 4 years ago - 3 comments

#40 - [vsg] add guidance on closing braces

Pull Request - State: closed - Opened by sjgitty over 4 years ago

#39 - [SV] Placement of closing parentheses in initializer lists

Issue - State: closed - Opened by imphil over 4 years ago - 3 comments

#38 - [style] update logical context guidance

Pull Request - State: closed - Opened by sjgitty over 4 years ago - 1 comment

#37 - [dv/style] Handling EOT with phase_ready_to_end

Pull Request - State: closed - Opened by udinator over 4 years ago - 5 comments

#36 - Clarify the usage of `parameter` in packages

Pull Request - State: closed - Opened by vogelpi over 4 years ago - 1 comment

#35 - [SystemVerilog] parameter vs. localparam in packages

Issue - State: closed - Opened by vogelpi almost 5 years ago - 5 comments

#34 - [dv style guide] More macro usage guidelines

Pull Request - State: closed - Opened by sriyerg almost 5 years ago - 5 comments

#33 - Copy-edit in DV styleguide (prefix -> suffix)

Pull Request - State: closed - Opened by rswarbrick almost 5 years ago

#32 - [doc] Three new optional styles added

Pull Request - State: closed - Opened by mwbranstad almost 5 years ago - 7 comments

#31 - Recommendations around xprop in simulations

Issue - State: open - Opened by GregAC almost 5 years ago - 11 comments

#30 - [UVM:styleguide] best end of test practices

Issue - State: closed - Opened by rasmus-madsen almost 5 years ago - 13 comments

#29 - Add guidance on functions and tasks

Pull Request - State: closed - Opened by GregAC almost 5 years ago - 5 comments

#28 - Use of functions and automatic

Issue - State: closed - Opened by GregAC almost 5 years ago - 6 comments

#27 - Add further advice around Xs and assertion use

Pull Request - State: closed - Opened by GregAC almost 5 years ago - 1 comment

#26 - Correct typos in VerilogCodingStyle.md

Pull Request - State: closed - Opened by felixonmars almost 5 years ago

#25 - [VSG] update Verilog Coding Style guidance on constants

Pull Request - State: closed - Opened by sjgitty almost 5 years ago - 3 comments

#24 - [verilog stlye guidelines] parameters should be all caps

Issue - State: closed - Opened by mwbranstad almost 5 years ago - 14 comments

#23 - Remove case-inside restriction

Pull Request - State: closed - Opened by msfschaffner almost 5 years ago

#22 - Initial commit of the Verilog DV style guide

Pull Request - State: closed - Opened by udinator almost 5 years ago - 15 comments

#21 - verilog style guidelines: Logical versus Bitwise

Issue - State: closed - Opened by mwbranstad almost 5 years ago - 15 comments

#20 - Remove wildcard import restriction

Pull Request - State: closed - Opened by eunchan about 5 years ago - 1 comment

#19 - Remove restriction of wildcard `import my_pkg::*;` inside the same module

Issue - State: closed - Opened by eunchan about 5 years ago - 7 comments

#18 - Remove case-inside construct restrictions in our style guide

Issue - State: closed - Opened by msfschaffner about 5 years ago - 12 comments
Labels: question

#17 - Fix emphasized paragraph style.

Pull Request - State: closed - Opened by msfschaffner about 5 years ago

#16 - Dealing with 'unavoidable' Xs to case statement inputs

Issue - State: closed - Opened by GregAC about 5 years ago - 6 comments

#15 - [Verilog] Revert guidance on avoiding localparam for derived parameters

Pull Request - State: closed - Opened by sjgitty about 5 years ago

#14 - [security] Provide RTL coding style guidance for security critical applications

Issue - State: open - Opened by msfschaffner about 5 years ago - 3 comments

#13 - Dealing with removing X in cases where consuming rather than producing X is the error

Issue - State: closed - Opened by GregAC about 5 years ago - 7 comments

#12 - [X/case] This refines guidance on usage of X and case statements

Pull Request - State: closed - Opened by msfschaffner about 5 years ago - 13 comments
Labels: documentation

#11 - [verilog] Extend section on comments with header-style

Pull Request - State: closed - Opened by msfschaffner about 5 years ago - 6 comments

#10 - Power and other implementation considerations

Issue - State: open - Opened by GregAC over 5 years ago - 5 comments

#9 - [verilog] Relax ternary parentheses

Pull Request - State: closed - Opened by vogelpi over 5 years ago - 4 comments

#8 - Discourage constant expressions in case statements

Issue - State: closed - Opened by imphil over 5 years ago - 10 comments

#7 - [verilog] Drop references to TODO and DEPRECATED comment formatting

Pull Request - State: closed - Opened by asb over 5 years ago

#6 - Dead link to deprecation comments

Issue - State: closed - Opened by MarekPikula over 5 years ago - 1 comment

#5 - [DV] Codify Verification Coding Style guidelines

Issue - State: closed - Opened by sjgitty over 5 years ago - 2 comments
Labels: documentation

#4 - [SystemVerilog] Macro naming convention

Issue - State: closed - Opened by sriyerg over 5 years ago - 9 comments

#3 - [SystemVerilog] Create style guide torture test

Issue - State: open - Opened by imphil over 5 years ago - 1 comment

#2 - [verilog] convert coding style recommendation to two spaces

Pull Request - State: closed - Opened by sjgitty over 5 years ago

#1 - [Verilog Style-Guide] Use 4 space indent only for wrapping long lines

Issue - State: closed - Opened by sjgitty over 5 years ago - 2 comments

GitHub / lowrisc/style-guides issues and pull requests