lowrisc/ibex issues and pull requests

#100 - [tracking] Pass RISC-V compliance test suite

Issue - State: closed - Opened by imphil over 5 years ago - 16 comments
Labels: Type:Task, Component:DV

#100 - [tracking] Pass RISC-V compliance test suite

Issue - State: closed - Opened by imphil over 5 years ago - 16 comments
Labels: Type:Task, Component:DV

#99 - Run RISC-V Compliance tests through Verilator

Issue - State: closed - Opened by imphil over 5 years ago - 10 comments
Labels: Type:Enhancement, Component:DV

#99 - Run RISC-V Compliance tests through Verilator

Issue - State: closed - Opened by imphil over 5 years ago - 10 comments
Labels: Type:Enhancement, Component:DV

#98 - when will ibex pass some of the compliance tests

Issue - State: closed - Opened by simon5656 over 5 years ago - 1 comment
Labels: Type:Question

#98 - when will ibex pass some of the compliance tests

Issue - State: closed - Opened by simon5656 over 5 years ago - 1 comment
Labels: Type:Question

#97 - Implement the mscratch CSR

Issue - State: closed - Opened by imphil over 5 years ago
Labels: Good First Issue, Component:RTL

#97 - Implement the mscratch CSR

Issue - State: closed - Opened by imphil over 5 years ago
Labels: Good First Issue, Component:RTL

#96 - Boot Address

Issue - State: closed - Opened by eroom1966 over 5 years ago - 6 comments
Labels: Type:Question

#96 - Boot Address

Issue - State: closed - Opened by eroom1966 over 5 years ago - 6 comments
Labels: Type:Question

#95 - Clarify usage and requirements of register file versions

Pull Request - State: closed - Opened by vogelpi over 5 years ago - 1 comment

#95 - Clarify usage and requirements of register file versions

Pull Request - State: closed - Opened by vogelpi over 5 years ago - 1 comment

#94 - interrupt & interrupt_disable

Issue - State: closed - Opened by gautschimi over 5 years ago - 3 comments

#94 - interrupt & interrupt_disable

Issue - State: closed - Opened by gautschimi over 5 years ago - 3 comments

#93 - Clock gate for latch-based register file

Issue - State: closed - Opened by vogelpi over 5 years ago
Labels: Type:Bug, Component:Doc, Component:RTL

#93 - Clock gate for latch-based register file

Issue - State: closed - Opened by vogelpi over 5 years ago
Labels: Type:Bug, Component:Doc, Component:RTL

#92 - Expand word widths to keep Verilator lint checks happy

Pull Request - State: closed - Opened by jrrk over 5 years ago - 2 comments

#92 - Expand word widths to keep Verilator lint checks happy

Pull Request - State: closed - Opened by jrrk over 5 years ago - 2 comments

#91 - We need to document working versions of CAD tools

Issue - State: closed - Opened by jrrk over 5 years ago - 3 comments
Labels: Type:Task, Component:Tool-and-Build

#91 - We need to document working versions of CAD tools

Issue - State: closed - Opened by jrrk over 5 years ago - 3 comments
Labels: Type:Task, Component:Tool-and-Build

#90 - Implement sleep with wfi instruction

Issue - State: closed - Opened by imphil over 5 years ago - 3 comments
Labels: Type:Enhancement, Good First Issue, Component:RTL

#90 - Implement sleep with wfi instruction

Issue - State: closed - Opened by imphil over 5 years ago - 3 comments
Labels: Type:Enhancement, Good First Issue, Component:RTL

#89 - [tracking] Implement bit manipulation (B) RISC-V ISA extension

Issue - State: closed - Opened by imphil over 5 years ago - 35 comments
Labels: Type:Enhancement, Component:RTL

#89 - [tracking] Implement bit manipulation (B) RISC-V ISA extension

Issue - State: closed - Opened by imphil over 5 years ago - 35 comments
Labels: Type:Enhancement, Component:RTL

#88 - Add support for User (U) mode

Issue - State: closed - Opened by imphil over 5 years ago
Labels: Type:Enhancement, Component:RTL

#88 - Add support for User (U) mode

Issue - State: closed - Opened by imphil over 5 years ago
Labels: Type:Enhancement, Component:RTL

#87 - Test trap precision

Issue - State: open - Opened by imphil over 5 years ago - 4 comments
Labels: Type:Enhancement, Component:DV

#86 - Document trap precision

Issue - State: open - Opened by imphil over 5 years ago - 1 comment
Labels: Component:Doc, Component:RTL, Type:Task

#86 - Document trap precision

Issue - State: open - Opened by imphil over 5 years ago - 1 comment
Labels: Component:Doc, Component:RTL, Type:Task

#85 - Disable performance counters by default

Pull Request - State: closed - Opened by imphil over 5 years ago - 2 comments

#85 - Disable performance counters by default

Pull Request - State: closed - Opened by imphil over 5 years ago - 2 comments

#84 - Make sure CSR set/clear/write op only change the CSR during one cycle

Pull Request - State: closed - Opened by vogelpi over 5 years ago

#84 - Make sure CSR set/clear/write op only change the CSR during one cycle

Pull Request - State: closed - Opened by vogelpi over 5 years ago

#83 - Fix perf counters

Pull Request - State: closed - Opened by vogelpi over 5 years ago

#83 - Fix perf counters

Pull Request - State: closed - Opened by vogelpi over 5 years ago

#82 - Align data and instruction address output

Pull Request - State: closed - Opened by vogelpi over 5 years ago - 1 comment

#82 - Align data and instruction address output

Pull Request - State: closed - Opened by vogelpi over 5 years ago - 1 comment

#81 - Update doc

Pull Request - State: closed - Opened by vogelpi over 5 years ago

#81 - Update doc

Pull Request - State: closed - Opened by vogelpi over 5 years ago

#80 - Number of performance counters

Issue - State: closed - Opened by gautschimi over 5 years ago - 10 comments

#80 - Number of performance counters

Issue - State: closed - Opened by gautschimi over 5 years ago - 10 comments

#79 - Fix vim setting suggestion

Pull Request - State: closed - Opened by towoe over 5 years ago

#79 - Fix vim setting suggestion

Pull Request - State: closed - Opened by towoe over 5 years ago

#78 - Ibex example Arty A7-100T

Pull Request - State: closed - Opened by towoe over 5 years ago - 8 comments

#78 - Ibex example Arty A7-100T

Pull Request - State: closed - Opened by towoe over 5 years ago - 8 comments

#77 - Tracer

Pull Request - State: closed - Opened by towoe over 5 years ago - 13 comments

#77 - Tracer

Pull Request - State: closed - Opened by towoe over 5 years ago - 13 comments

#76 - Fix RVFI signal name

Pull Request - State: closed - Opened by towoe over 5 years ago - 1 comment

#76 - Fix RVFI signal name

Pull Request - State: closed - Opened by towoe over 5 years ago - 1 comment

#75 - Unaligned instruction fetch and data addresses

Issue - State: closed - Opened by AntonBabushkin over 5 years ago - 33 comments
Labels: Type:Bug, Component:RTL

#74 - Fix linting errors

Pull Request - State: closed - Opened by vogelpi over 5 years ago

#74 - Fix linting errors

Pull Request - State: closed - Opened by vogelpi over 5 years ago

#73 - [DV] Fix tcl path

Pull Request - State: closed - Opened by taoliug over 5 years ago

#73 - [DV] Fix tcl path

Pull Request - State: closed - Opened by taoliug over 5 years ago

#72 - Reference integration for FPGA

Issue - State: closed - Opened by imphil over 5 years ago - 2 comments
Labels: Type:Enhancement, Component:RTL

#72 - Reference integration for FPGA

Issue - State: closed - Opened by imphil over 5 years ago - 2 comments
Labels: Type:Enhancement, Component:RTL

#71 - [DV] Add coverage dump options

Pull Request - State: closed - Opened by taoliug over 5 years ago - 3 comments

#71 - [DV] Add coverage dump options

Pull Request - State: closed - Opened by taoliug over 5 years ago - 3 comments

#70 - Implement trap handling according to latest RISC-V spec

Issue - State: closed - Opened by davideschiavone over 5 years ago - 6 comments
Labels: Component:RTL, Type:Spec-Compliance

#70 - Implement trap handling according to latest RISC-V spec

Issue - State: closed - Opened by davideschiavone over 5 years ago - 6 comments
Labels: Component:RTL, Type:Spec-Compliance

#69 - Import riscv-dv @b4bd0c6cff0456111be966a11c1bd0aeec2d96e4

Pull Request - State: closed - Opened by taoliug over 5 years ago

#68 - Missing prim_clock_gating module

Issue - State: closed - Opened by darbaria over 5 years ago - 10 comments
Labels: Type:Enhancement, Component:RTL

#67 - Update documentation

Pull Request - State: closed - Opened by vogelpi over 5 years ago - 3 comments

#66 - Doc: Fix parameter names

Pull Request - State: closed - Opened by imphil over 5 years ago - 2 comments

#65 - Update documentation external link

Pull Request - State: closed - Opened by towoe over 5 years ago

#64 - Evaluate the feasibility of parameterising ibex by XLEN

Issue - State: open - Opened by asb over 5 years ago - 4 comments
Labels: Type:Enhancement, Component:RTL

#63 - Replace block diagram with updated version

Issue - State: closed - Opened by imphil over 5 years ago - 1 comment
Labels: Type:Enhancement, Component:Doc

#62 - Switch ibex_tracer to use RVFI

Issue - State: closed - Opened by imphil over 5 years ago
Labels: Type:Enhancement, Component:RTL

#61 - RISC-V Formal Interface

Pull Request - State: closed - Opened by towoe over 5 years ago - 10 comments

#60 - [tracking] Synthesize Ibex with Yosys

Issue - State: open - Opened by imphil over 5 years ago - 7 comments
Labels: Component:RTL, Type:Task, Component:DV

#59 - Doc: Switch back to upstream Sphinx

Pull Request - State: closed - Opened by imphil over 5 years ago

#58 - fix ibex TB top compilation issue

Pull Request - State: closed - Opened by taoliug over 5 years ago

#57 - Update google_riscv-dv to be14080

Pull Request - State: closed - Opened by taoliug over 5 years ago - 1 comment

#56 - Add TB for ibex core

Pull Request - State: closed - Opened by taoliug over 5 years ago - 3 comments

#55 - Update google_riscv-dv to 215e064

Pull Request - State: closed - Opened by taoliug over 5 years ago - 1 comment

#54 - Fix decoding of C.LI, C.LUI, C.SRLI, C.SRAI, C.SSLI

Pull Request - State: closed - Opened by vogelpi over 5 years ago

#53 - Perf counters & CSRs

Pull Request - State: closed - Opened by vogelpi over 5 years ago - 3 comments

#52 - Add riscv-dv vendor in script and patches

Pull Request - State: closed - Opened by taoliug over 5 years ago - 5 comments

#51 - HINT instruction decoding issue - 0x7065

Issue - State: closed - Opened by taoliug over 5 years ago
Labels: Type:Bug, Component:RTL

#50 - Fix non-unique case bug in tracer.

Pull Request - State: closed - Opened by ikarageo over 5 years ago

#49 - Code cleanup

Pull Request - State: closed - Opened by vogelpi over 5 years ago

#48 - Compressed hints

Pull Request - State: closed - Opened by imphil over 5 years ago - 1 comment

#47 - Code cleanup

Pull Request - State: closed - Opened by vogelpi over 5 years ago

#46 - Decode HINT as NOP

Issue - State: closed - Opened by imphil over 5 years ago - 3 comments
Labels: Type:Bug, Component:RTL

#45 - Code cleanup

Pull Request - State: closed - Opened by vogelpi over 5 years ago

#44 - Missing description of input signal from documentation.

Issue - State: closed - Opened by ikarageo over 5 years ago - 2 comments
Labels: Type:Bug, Component:Doc

#43 - Replace non-unique `case` constructs by `unique case`

Issue - State: closed - Opened by vogelpi over 5 years ago
Labels: Component:RTL, Type:Cleanup

#42 - Typo fix in muldiv: Reminder->Remainder

Pull Request - State: closed - Opened by wallento over 5 years ago - 1 comment

#41 - Switch back to upstream Sphinx package

Issue - State: closed - Opened by imphil over 5 years ago - 2 comments
Labels: Component:Doc, Type:Task

#40 - Fix synthesis ikarageo

Pull Request - State: closed - Opened by imphil over 5 years ago

#39 - Code cleanup

Pull Request - State: closed - Opened by vogelpi over 5 years ago

#38 - Fix unsynthesizable construct and missing signal for tracer

Pull Request - State: closed - Opened by ikarageo over 5 years ago - 3 comments

#37 - Temporarily switch to custom sphinx

Pull Request - State: closed - Opened by wallento over 5 years ago - 2 comments

#36 - Fix wavedrom versions

Pull Request - State: closed - Opened by wallento over 5 years ago - 3 comments

#35 - Fix missing enum casts

Pull Request - State: closed - Opened by vogelpi over 5 years ago

#34 - Illegal assignment of logic variable to enum type port

Issue - State: closed - Opened by ikarageo over 5 years ago - 1 comment

#33 - Enum assignment cast

Issue - State: closed - Opened by towoe over 5 years ago - 6 comments

#32 - Code cleanup

Pull Request - State: closed - Opened by vogelpi over 5 years ago - 1 comment

#31 - Code cleanup, addresses #150 in stwg-base

Pull Request - State: closed - Opened by vogelpi over 5 years ago - 5 comments

#30 - Cleanup: Remove REG_* defines from ibex_id_stage

Issue - State: closed - Opened by imphil over 5 years ago - 7 comments
Labels: Good First Issue, Component:RTL, Type:Cleanup

GitHub / lowrisc/ibex issues and pull requests