lowrisc/ibex issues and pull requests

#2247 - Fix typo in comment in ibex_id_stage.sv

Pull Request - State: closed - Opened by KatCe 6 days ago

#2246 - mtvec.BASE aligned to 256 bytes bug

Issue - State: closed - Opened by ha0lyu 7 days ago - 1 comment
Labels: Type:Bug

#2245 - Formal cleanup

Pull Request - State: open - Opened by marnovandermaas 9 days ago - 1 comment

#2244 - How reliable is the reference model of cosim?

Issue - State: open - Opened by ha0lyu 10 days ago - 2 comments
Labels: Type:Question

#2243 - [ibex_tracer] Use static variables in always/final blocks

Pull Request - State: closed - Opened by Razer6 13 days ago - 2 comments

#2242 - [dv] tb_cs_registers golden-model error in ePMP extension

Issue - State: open - Opened by ZhongYic00 15 days ago
Labels: Type:Bug

#2241 - [rtl] Drive oh_raddr_*_err if RdataMuxCheck=0

Pull Request - State: closed - Opened by rswarbrick 16 days ago
Labels: Component:RTL

#2240 - fix: compressed decoder

Pull Request - State: open - Opened by ha0lyu 16 days ago - 1 comment

#2239 - Undriven signal in ibex_register_file_fpga.sv

Issue - State: closed - Opened by shareefj 19 days ago - 1 comment
Labels: Type:Bug

#2238 - How to use Ibex with mainline fusesoc

Issue - State: open - Opened by shareefj 19 days ago - 2 comments
Labels: Type:Question

#2237 - Writing `mseccfg`=0x1 will jump to `_vectors_start`

Issue - State: open - Opened by ha0lyu 20 days ago - 6 comments
Labels: Type:Bug

#2236 - simulator report error

Issue - State: open - Opened by ha0lyu 29 days ago - 9 comments
Labels: Type:Bug

#2235 - Facing issue while running using Questa

Issue - State: open - Opened by Priyanshumishra77 about 1 month ago
Labels: Type:Question

#2234 - Update core_ibex_pmp_fcov_if.sv

Pull Request - State: closed - Opened by Priyanshumishra77 about 1 month ago

#2233 - [dv] Verify access to Debug Module in debug mode even if disallowed by PMP

Issue - State: open - Opened by andreaskurth about 1 month ago

#2232 - [rtl,pmp] Allow all accesses to Debug Module in debug mode

Pull Request - State: closed - Opened by andreaskurth about 1 month ago - 5 comments

#2231 - [rvfi] rvfi_pc_wdata doesn't consider mret/dret

Issue - State: open - Opened by georgerennie about 1 month ago
Labels: Type:Bug

#2230 - [regfile_fpga] oh_raddr_*_err signals unassigned if RdataMuxCheck=0

Issue - State: open - Opened by glaserf about 2 months ago
Labels: Type:Bug

#2229 - Revert "[rtl] Fix counter reset value on FPGA"

Pull Request - State: closed - Opened by nasahlpa about 2 months ago

#2228 - [rtl] Fix non-DSP reset in ibex_counter

Pull Request - State: closed - Opened by nasahlpa about 2 months ago - 3 comments

#2227 - ibex_pcounts: resolve uninitialize warning

Pull Request - State: closed - Opened by marnovandermaas about 2 months ago

#2226 - [rtl] Fix counter reset value on FPGA

Pull Request - State: closed - Opened by nasahlpa about 2 months ago

#2225 - [ci] remove Azure Pipelines

Pull Request - State: closed - Opened by nbdd0121 2 months ago

#2224 - [rtl] Fix zero value in FPGA RF

Pull Request - State: closed - Opened by nasahlpa 2 months ago

#2222 - Ask a question related to Ibex

Issue - State: open - Opened by kalabYibeltal 2 months ago - 3 comments
Labels: Type:Question

#2203 - Problem with ibex_alu.sv when synthesis with genus cadence

Issue - State: closed - Opened by cern143 5 months ago - 2 comments
Labels: Type:Bug

#2156 - Proof-of-concept Nix environments for Ibex development

Pull Request - State: open - Opened by hcallahan-lowrisc 10 months ago - 1 comment

#2071 - make[1]: *** [out/metadata/tb.compile.stamp] Error 2

Issue - State: open - Opened by cllll402 over 1 year ago - 7 comments
Labels: Type:Question

#2065 - Ask a question related to Ibex, behavior simulation error in Vivado

Issue - State: open - Opened by twyayaya over 1 year ago - 1 comment
Labels: Type:Question

#1858 - [docs] Clean up line breaks #1191

Pull Request - State: open - Opened by kal-ne over 2 years ago

#1679 - Simulating Arty A7 35 example in Vivado causes error due to hack in ibex_if_stage.sv

Issue - State: open - Opened by epsilon537 over 2 years ago - 3 comments
Labels: Type:Bug

#1430 - RISC-V A atomic extension support in Ibex

Issue - State: closed - Opened by jtate-google over 3 years ago - 5 comments
Labels: Type:Enhancement, Type:Question, Component:RTL

#1191 - [docs] Clean up line breaks

Issue - State: open - Opened by GregAC about 4 years ago - 6 comments
Labels: Good First Issue, Component:Doc, Type:Cleanup

#100 - [tracking] Pass RISC-V compliance test suite

Issue - State: closed - Opened by imphil over 5 years ago - 16 comments
Labels: Type:Task, Component:DV

#100 - [tracking] Pass RISC-V compliance test suite

Issue - State: closed - Opened by imphil over 5 years ago - 16 comments
Labels: Type:Task, Component:DV

#99 - Run RISC-V Compliance tests through Verilator

Issue - State: closed - Opened by imphil over 5 years ago - 10 comments
Labels: Type:Enhancement, Component:DV

#99 - Run RISC-V Compliance tests through Verilator

Issue - State: closed - Opened by imphil over 5 years ago - 10 comments
Labels: Type:Enhancement, Component:DV

#98 - when will ibex pass some of the compliance tests

Issue - State: closed - Opened by simon5656 over 5 years ago - 1 comment
Labels: Type:Question

#98 - when will ibex pass some of the compliance tests

Issue - State: closed - Opened by simon5656 over 5 years ago - 1 comment
Labels: Type:Question

#97 - Implement the mscratch CSR

Issue - State: closed - Opened by imphil over 5 years ago
Labels: Good First Issue, Component:RTL

#97 - Implement the mscratch CSR

Issue - State: closed - Opened by imphil over 5 years ago
Labels: Good First Issue, Component:RTL

#96 - Boot Address

Issue - State: closed - Opened by eroom1966 over 5 years ago - 6 comments
Labels: Type:Question

#96 - Boot Address

Issue - State: closed - Opened by eroom1966 over 5 years ago - 6 comments
Labels: Type:Question

#95 - Clarify usage and requirements of register file versions

Pull Request - State: closed - Opened by vogelpi over 5 years ago - 1 comment

#95 - Clarify usage and requirements of register file versions

Pull Request - State: closed - Opened by vogelpi over 5 years ago - 1 comment

#94 - interrupt & interrupt_disable

Issue - State: closed - Opened by gautschimi over 5 years ago - 3 comments

#94 - interrupt & interrupt_disable

Issue - State: closed - Opened by gautschimi over 5 years ago - 3 comments

#93 - Clock gate for latch-based register file

Issue - State: closed - Opened by vogelpi over 5 years ago
Labels: Type:Bug, Component:Doc, Component:RTL

#93 - Clock gate for latch-based register file

Issue - State: closed - Opened by vogelpi over 5 years ago
Labels: Type:Bug, Component:Doc, Component:RTL

#92 - Expand word widths to keep Verilator lint checks happy

Pull Request - State: closed - Opened by jrrk over 5 years ago - 2 comments

#92 - Expand word widths to keep Verilator lint checks happy

Pull Request - State: closed - Opened by jrrk over 5 years ago - 2 comments

#91 - We need to document working versions of CAD tools

Issue - State: closed - Opened by jrrk over 5 years ago - 3 comments
Labels: Type:Task, Component:Tool-and-Build

#91 - We need to document working versions of CAD tools

Issue - State: closed - Opened by jrrk over 5 years ago - 3 comments
Labels: Type:Task, Component:Tool-and-Build

#90 - Implement sleep with wfi instruction

Issue - State: closed - Opened by imphil over 5 years ago - 3 comments
Labels: Type:Enhancement, Good First Issue, Component:RTL

#90 - Implement sleep with wfi instruction

Issue - State: closed - Opened by imphil over 5 years ago - 3 comments
Labels: Type:Enhancement, Good First Issue, Component:RTL

#89 - [tracking] Implement bit manipulation (B) RISC-V ISA extension

Issue - State: closed - Opened by imphil over 5 years ago - 35 comments
Labels: Type:Enhancement, Component:RTL

#89 - [tracking] Implement bit manipulation (B) RISC-V ISA extension

Issue - State: closed - Opened by imphil over 5 years ago - 35 comments
Labels: Type:Enhancement, Component:RTL

#88 - Add support for User (U) mode

Issue - State: closed - Opened by imphil over 5 years ago
Labels: Type:Enhancement, Component:RTL

#88 - Add support for User (U) mode

Issue - State: closed - Opened by imphil over 5 years ago
Labels: Type:Enhancement, Component:RTL

#87 - Test trap precision

Issue - State: open - Opened by imphil over 5 years ago - 4 comments
Labels: Type:Enhancement, Component:DV

#86 - Document trap precision

Issue - State: open - Opened by imphil over 5 years ago - 1 comment
Labels: Component:Doc, Component:RTL, Type:Task

#86 - Document trap precision

Issue - State: open - Opened by imphil over 5 years ago - 1 comment
Labels: Component:Doc, Component:RTL, Type:Task

#85 - Disable performance counters by default

Pull Request - State: closed - Opened by imphil over 5 years ago - 2 comments

#85 - Disable performance counters by default

Pull Request - State: closed - Opened by imphil over 5 years ago - 2 comments

#84 - Make sure CSR set/clear/write op only change the CSR during one cycle

Pull Request - State: closed - Opened by vogelpi over 5 years ago

#84 - Make sure CSR set/clear/write op only change the CSR during one cycle

Pull Request - State: closed - Opened by vogelpi over 5 years ago

#83 - Fix perf counters

Pull Request - State: closed - Opened by vogelpi over 5 years ago

#83 - Fix perf counters

Pull Request - State: closed - Opened by vogelpi over 5 years ago

#82 - Align data and instruction address output

Pull Request - State: closed - Opened by vogelpi over 5 years ago - 1 comment

#82 - Align data and instruction address output

Pull Request - State: closed - Opened by vogelpi over 5 years ago - 1 comment

#81 - Update doc

Pull Request - State: closed - Opened by vogelpi over 5 years ago

#81 - Update doc

Pull Request - State: closed - Opened by vogelpi over 5 years ago

#80 - Number of performance counters

Issue - State: closed - Opened by gautschimi over 5 years ago - 10 comments

#80 - Number of performance counters

Issue - State: closed - Opened by gautschimi over 5 years ago - 10 comments

#79 - Fix vim setting suggestion

Pull Request - State: closed - Opened by towoe over 5 years ago

#79 - Fix vim setting suggestion

Pull Request - State: closed - Opened by towoe over 5 years ago

#78 - Ibex example Arty A7-100T

Pull Request - State: closed - Opened by towoe over 5 years ago - 8 comments

#78 - Ibex example Arty A7-100T

Pull Request - State: closed - Opened by towoe over 5 years ago - 8 comments

#77 - Tracer

Pull Request - State: closed - Opened by towoe over 5 years ago - 13 comments

#77 - Tracer

Pull Request - State: closed - Opened by towoe over 5 years ago - 13 comments

#76 - Fix RVFI signal name

Pull Request - State: closed - Opened by towoe over 5 years ago - 1 comment

#76 - Fix RVFI signal name

Pull Request - State: closed - Opened by towoe over 5 years ago - 1 comment

#75 - Unaligned instruction fetch and data addresses

Issue - State: closed - Opened by AntonBabushkin over 5 years ago - 33 comments
Labels: Type:Bug, Component:RTL

#74 - Fix linting errors

Pull Request - State: closed - Opened by vogelpi over 5 years ago

#74 - Fix linting errors

Pull Request - State: closed - Opened by vogelpi over 5 years ago

#73 - [DV] Fix tcl path

Pull Request - State: closed - Opened by taoliug over 5 years ago

#73 - [DV] Fix tcl path

Pull Request - State: closed - Opened by taoliug over 5 years ago

#72 - Reference integration for FPGA

Issue - State: closed - Opened by imphil over 5 years ago - 2 comments
Labels: Type:Enhancement, Component:RTL

#72 - Reference integration for FPGA

Issue - State: closed - Opened by imphil over 5 years ago - 2 comments
Labels: Type:Enhancement, Component:RTL

#71 - [DV] Add coverage dump options

Pull Request - State: closed - Opened by taoliug over 5 years ago - 3 comments

#71 - [DV] Add coverage dump options

Pull Request - State: closed - Opened by taoliug over 5 years ago - 3 comments

#70 - Implement trap handling according to latest RISC-V spec

Issue - State: closed - Opened by davideschiavone over 5 years ago - 6 comments
Labels: Component:RTL, Type:Spec-Compliance

#70 - Implement trap handling according to latest RISC-V spec

Issue - State: closed - Opened by davideschiavone over 5 years ago - 6 comments
Labels: Component:RTL, Type:Spec-Compliance

#69 - Import riscv-dv @b4bd0c6cff0456111be966a11c1bd0aeec2d96e4

Pull Request - State: closed - Opened by taoliug over 5 years ago

#68 - Missing prim_clock_gating module

Issue - State: closed - Opened by darbaria over 5 years ago - 10 comments
Labels: Type:Enhancement, Component:RTL

#67 - Update documentation

Pull Request - State: closed - Opened by vogelpi over 5 years ago - 3 comments

#66 - Doc: Fix parameter names

Pull Request - State: closed - Opened by imphil over 5 years ago - 2 comments

#65 - Update documentation external link

Pull Request - State: closed - Opened by towoe over 5 years ago

#64 - Evaluate the feasibility of parameterising ibex by XLEN

Issue - State: open - Opened by asb over 5 years ago - 4 comments
Labels: Type:Enhancement, Component:RTL

#63 - Replace block diagram with updated version

Issue - State: closed - Opened by imphil over 5 years ago - 1 comment
Labels: Type:Enhancement, Component:Doc

GitHub / lowrisc/ibex issues and pull requests