Ecosyste.ms: Issues

An open API service for providing issue and pull request metadata for open source projects.

GitHub / llvm / circt issue stats

Last synced: about 13 hours ago

Total issues: 374
Total pull requests: 1,451
Average time to close issues: 3 months
Average time to close pull requests: 18 days
Total issue authors: 79
Total pull request authors: 82
Average comments per issue: 1.63
Average comments per pull request: 1.36
Merged pull requests: 1,217
Bot issues: 0
Bot pull requests: 0

Past year issues: 328
Past year pull requests: 1,232
Past year average time to close issues: 19 days
Past year average time to close pull requests: 7 days
Past year issue authors: 69
Past year pull request authors: 76
Past year average comments per issue: 1.58
Past year average comments per pull request: 1.27
Past year merged pull requests: 1,052
Past year bot issues: 0
Past year bot pull requests: 0

More repo stats: https://repos.ecosyste.ms/hosts/GitHub/repositories/llvm/circt
JSON API: https://issues.ecosyste.ms/api/v1/hosts/GitHub/repositories/llvm%2Fcirct

Issue Author Associations

  • Contributor (199, 53.21%)
  • Member (131, 35.03%)
  • None (43, 11.50%)
  • Collaborator (1, 0.27%)

Pull Request Author Associations

  • Contributor (992, 68.37%)
  • Member (436, 30.05%)
  • None (23, 1.59%)

Top Issue Authors

Top Pull Request Authors


All Maintainers

Active Maintainers


Top Issue Labels

  • FIRRTL (117)
  • bug (90)
  • good first issue (22)
  • enhancement (17)
  • Moore (16)
  • LLHD (15)
  • ESI (12)
  • Arc (10)
  • HW (9)
  • ImportVerilog (8)
  • Calyx (8)
  • documentation (8)
  • Seq (7)
  • verif (7)
  • Comb (6)
  • RTG (5)
  • Scheduling (5)
  • ExportVerilog (4)
  • HandshakeToDC (4)
  • Debug (4)
  • HWArith (3)
  • SMT (3)
  • Simulator (3)
  • HandshakeToHW (2)
  • DC (2)
  • OM (2)
  • Handshake (2)
  • Verilog/SystemVerilog (2)
  • Ibis (2)
  • duplicate (1)

Top Pull Request Labels

  • Moore (101)
  • FIRRTL (91)
  • RTG (69)
  • ESI (66)
  • verif (29)
  • bug (26)
  • Calyx (25)
  • ImportVerilog (24)
  • Verilog/SystemVerilog (23)
  • LLHD (23)
  • PyCDE (18)
  • Arc (16)
  • Handshake (11)
  • HW (11)
  • documentation (8)
  • Comb (7)
  • Ibis (5)
  • DC (5)
  • Seq (4)
  • Pipeline (4)
  • enhancement (4)
  • Python (3)
  • SMT (3)
  • HWArith (2)
  • Scheduling (2)
  • Debug (2)
  • HandshakeToDC (2)
  • ExportVerilog (2)
  • Kanagawa (1)
  • SV (1)