Ecosyste.ms: Issues
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GitHub / ispras/hdl-benchmarks issues and pull requests
#11 - Incorrectly defined aux file 'altsyncram.v' in 'oc_oc8051' ('quip' benchmark)
Issue -
State: closed - Opened by iagrigorov 4 months ago
- 3 comments
#10 - Missing module 'RAM16X1D' (in 'iwls05' benchmark in project 'pci')
Issue -
State: closed - Opened by iagrigorov 4 months ago
- 1 comment
#9 - bugfix: width mismatch on port 'T_PLLsel' of reference to 'PLL' in 'TOP'
Pull Request -
State: closed - Opened by phyzhenli almost 2 years ago
- 1 comment
#8 - add necessary GTECH_* statements
Pull Request -
State: closed - Opened by phyzhenli almost 2 years ago
- 1 comment
#7 - fix bugs for iwls05/faraday/DSP block
Pull Request -
State: closed - Opened by phyzhenli about 2 years ago
- 1 comment
#7 - fix bugs for iwls05/faraday/DSP block
Pull Request -
State: closed - Opened by phyzhenli about 2 years ago
- 1 comment
#6 - add case default to avoid latch
Pull Request -
State: closed - Opened by phyzhenli about 2 years ago
- 1 comment
#5 - Look for duplicates in RTL & remove them, if needed
Issue -
State: open - Opened by ssmolov almost 3 years ago
- 1 comment
#4 - test results collecting in CSV
Issue -
State: closed - Opened by ssmolov almost 3 years ago
- 1 comment
#3 - Verilog2SMV should generate MSV files with names of original Verilog files
Issue -
State: closed - Opened by ssmolov about 3 years ago
- 1 comment
#2 - Bash scripts for EBMC\SymbiYosys\Verilog2SMV can't extract names of several Verilog modules
Issue -
State: closed - Opened by ssmolov over 5 years ago
- 1 comment
#1 - scripts for commercial FV tools running
Issue -
State: closed - Opened by ssmolov over 5 years ago
- 1 comment