Ecosyste.ms: Issues
An open API service for providing issue and pull request metadata for open source projects.
GitHub / intel/rohd issues and pull requests
#460 - Add youtube channel link to Readme.md
Pull Request -
State: open - Opened by quekyj about 1 year ago
#459 - Make conditional assign a little more optimistic with invalid values
Pull Request -
State: closed - Opened by mkorbel1 about 1 year ago
#458 - Fix bugs in `LogicStructure` instrumentation calls to `packed` and `changed` issues across `Simulator.reset`
Pull Request -
State: closed - Opened by mkorbel1 about 1 year ago
#457 - Non-synthesizable APIs on `LogicStructure` rely on `packed`
Issue -
State: closed - Opened by mkorbel1 about 1 year ago
Labels: bug
#456 - Issue #377: assign a logic subset to logic (array)
Pull Request -
State: open - Opened by RPG-coder-intc about 1 year ago
#455 - Make `Simulator.endSimulation` return a `Future`
Pull Request -
State: closed - Opened by mkorbel1 about 1 year ago
#454 - Fix defaultNextState diagram generation in FSM
Pull Request -
State: closed - Opened by mkorbel1 about 1 year ago
#453 - Update some pages of the user guide
Pull Request -
State: closed - Opened by mkorbel1 about 1 year ago
#452 - Update default permissions in GH actions
Pull Request -
State: closed - Opened by mkorbel1 about 1 year ago
#451 - Add a way to run the Simulator "until" a certain time (without ending the simulation)
Issue -
State: open - Opened by mkorbel1 about 1 year ago
Labels: enhancement, good first issue
#450 - Add a utility for "waiting" a certain amount of time in the Simulator.
Issue -
State: open - Opened by mkorbel1 about 1 year ago
Labels: enhancement, good first issue
#448 - Update counter example to be simpler and a better reference
Pull Request -
State: closed - Opened by mkorbel1 about 1 year ago
#447 - Pipeline fixes and improvements
Pull Request -
State: closed - Opened by mkorbel1 about 1 year ago
#446 - Simulation Bug: WaveDumper Function Must Be Placed Before Simulator Class to Prevent Errors
Issue -
State: open - Opened by quekyj about 1 year ago
Labels: bug
#445 - Support compiling ROHD to JavaScript
Pull Request -
State: closed - Opened by mkorbel1 about 1 year ago
#444 - Improve lint avoidance for width expansion
Issue -
State: open - Opened by mkorbel1 about 1 year ago
- 1 comment
Labels: enhancement
#443 - Optimize performance of `Combinational.ssa` driver search
Pull Request -
State: closed - Opened by mkorbel1 about 1 year ago
#442 - Absolute value
Pull Request -
State: closed - Opened by dmetis about 1 year ago
#439 - Signal naming improvements
Pull Request -
State: closed - Opened by mkorbel1 over 1 year ago
#438 - Get a Logic of a Logic List via an index
Pull Request -
State: closed - Opened by RPG-coder-intc over 1 year ago
- 1 comment
#437 - Vscode extension
Pull Request -
State: open - Opened by quekyj over 1 year ago
#436 - Add support for edalize
Issue -
State: open - Opened by mkorbel1 over 1 year ago
Labels: enhancement
#435 - ROHD Module Hierarchy and Signals Visualization (Flutter UI)
Pull Request -
State: open - Opened by quekyj over 1 year ago
#434 - Allow `SynthBuilder` to accept multiple `Module`s.
Issue -
State: open - Opened by mkorbel1 over 1 year ago
Labels: enhancement
#433 - `PairInterface` should enable receiving/driving all sub-interfaces as well
Issue -
State: open - Opened by mkorbel1 over 1 year ago
Labels: enhancement
#432 - Add capability to `PairInterface` to modify naming at time of `addSubInterface`
Issue -
State: open - Opened by mkorbel1 over 1 year ago
Labels: enhancement
#431 - Add a quick way to instantiate simple external SystemVerilog modules.
Issue -
State: open - Opened by mkorbel1 over 1 year ago
Labels: enhancement
#430 - Improve documentation on instantiating SystemVerilog modules
Issue -
State: open - Opened by mkorbel1 over 1 year ago
Labels: documentation
#429 - Avoid module creation for simple constant scenarios in gates
Issue -
State: open - Opened by mkorbel1 over 1 year ago
- 2 comments
Labels: enhancement
#428 - Simulator optimization: don't simulate signals that don't matter (optionally)
Issue -
State: open - Opened by mkorbel1 over 1 year ago
Labels: enhancement
#427 - Add capabilities to transpose `LogicArray`s
Issue -
State: open - Opened by mkorbel1 over 1 year ago
Labels: enhancement
#426 - Add example on how to use Logic Array assignment would be good
Issue -
State: open - Opened by quekyj over 1 year ago
- 2 comments
Labels: documentation, enhancement
#424 - Pipeline must provide access to inputs of a given stage.
Issue -
State: open - Opened by kimmeljo over 1 year ago
- 6 comments
Labels: bug, enhancement
#423 - Fix bug where generated SV has lint issues with plus and shift-left due to SV width expansion
Pull Request -
State: closed - Opened by mkorbel1 over 1 year ago
#422 - Logic value
Pull Request -
State: open - Opened by mjayasim9 over 1 year ago
#421 - Allow multiple nonblocking assignments, fix #321
Pull Request -
State: closed - Opened by mkorbel1 over 1 year ago
#420 - Sort ports and internal signals, fix #395
Pull Request -
State: closed - Opened by mkorbel1 over 1 year ago
#419 - `Logic.zeroExtend` should return `this` if `width` is the same as `newWidth`, and `Swizzle` optimization in SV generation
Issue -
State: open - Opened by mkorbel1 over 1 year ago
Labels: bug, good first issue
#417 - Update to use new runners in github actions
Pull Request -
State: open - Opened by mkorbel1 over 1 year ago
#416 - Mark inputs as protected in `Module`
Pull Request -
State: closed - Opened by mkorbel1 over 1 year ago
#415 - Allow deploy docs (temporary PR)
Pull Request -
State: closed - Opened by mkorbel1 over 1 year ago
#414 - Updates to FSM and Pipeline abstractions and documentation
Pull Request -
State: closed - Opened by mkorbel1 over 1 year ago
#413 - Cleanup some doc and comments
Pull Request -
State: closed - Opened by mkorbel1 over 1 year ago
#412 - Fixes and improvements related to shifts
Pull Request -
State: closed - Opened by mkorbel1 over 1 year ago
#411 - LogicValue division with negative numbers doesn't work as expected
Issue -
State: closed - Opened by mkorbel1 over 1 year ago
- 1 comment
Labels: bug
#410 - Reset for flops and try ports
Pull Request -
State: closed - Opened by mkorbel1 over 1 year ago
#409 - `StateMachine` abstraction should expose mapping of identifiers to state index
Issue -
State: closed - Opened by mkorbel1 over 1 year ago
Labels: enhancement
#408 - Optimize generation of SV for bus subset to eliminate extraneous assign statements
Issue -
State: closed - Opened by mkorbel1 over 1 year ago
Labels: enhancement
#407 - Chapter 9 - Tutorials on ROHD Verification Framework
Pull Request -
State: closed - Opened by quekyj over 1 year ago
- 2 comments
#406 - Add multi-trigger (e.g. async reset) to abstractions
Issue -
State: closed - Opened by mkorbel1 over 1 year ago
Labels: enhancement, good first issue
#405 - Add `tryInput` and `tryOutput` that returns null if `input` and `output` don't exist
Issue -
State: closed - Opened by mkorbel1 over 1 year ago
Labels: enhancement, good first issue
#404 - Shifting large bit vectors (width > 64) can sometimes result in unexpected Dart exception.
Issue -
State: closed - Opened by kimmeljo over 1 year ago
- 1 comment
Labels: bug, good first issue
#403 - Unique case with multiple match behavior
Pull Request -
State: closed - Opened by dmetis over 1 year ago
#402 - Lint cleanup
Pull Request -
State: closed - Opened by mkorbel1 over 1 year ago
#400 - The content of FSM in website user guide is confusing
Issue -
State: closed - Opened by quekyj over 1 year ago
Labels: documentation, enhancement
#399 - Add chapter 8 tutorials
Pull Request -
State: closed - Opened by quekyj over 1 year ago
#398 - Fix blog link in README
Pull Request -
State: closed - Opened by mkorbel1 over 1 year ago
#397 - Fix some sensitive tests to be more robust
Pull Request -
State: closed - Opened by mkorbel1 over 1 year ago
#396 - Make "expected" message in SV testbench from SimCompare include width for invalid signals
Issue -
State: open - Opened by mkorbel1 over 1 year ago
Labels: enhancement
#395 - Sort ports in generated outputs
Issue -
State: closed - Opened by mkorbel1 over 1 year ago
Labels: enhancement
#394 - Generate RTL for both classes even when two classes have identical contents
Issue -
State: closed - Opened by sshankar4 over 1 year ago
- 2 comments
Labels: bug
#393 - Gates should output X (never Z) when inputs are invalid
Pull Request -
State: closed - Opened by dmetis over 1 year ago
- 2 comments
#391 - Fix bugs where SSA could potentially generate inferred latches
Pull Request -
State: closed - Opened by mkorbel1 over 1 year ago
#390 - Fix bug where FSM may cause inferred latch
Pull Request -
State: closed - Opened by mkorbel1 over 1 year ago
#389 - Add branch coverage to script
Pull Request -
State: closed - Opened by mkorbel1 over 1 year ago
#388 - Refactor docs and README for website
Pull Request -
State: closed - Opened by mkorbel1 over 1 year ago
- 1 comment
#387 - Fix bug with SSA reuse of signals
Pull Request -
State: closed - Opened by mkorbel1 over 1 year ago
- 2 comments
#386 - Cases
Pull Request -
State: closed - Opened by mjayasim9 over 1 year ago
- 1 comment
#385 - Add `previousValue` to `Logic`
Pull Request -
State: closed - Opened by mkorbel1 over 1 year ago
#384 - Wave dumping with `LogicArray`s and `LogicStructure`s
Issue -
State: closed - Opened by mkorbel1 over 1 year ago
- 3 comments
Labels: enhancement
#383 - Fix #382, if block exceptions when else is wrong
Pull Request -
State: closed - Opened by mkorbel1 over 1 year ago
#382 - An `If.block` with only one `Else` in it does not flag an error
Issue -
State: closed - Opened by mkorbel1 over 1 year ago
Labels: bug
#381 - Issue#257: Added flop like function to construct FlipFlop
Pull Request -
State: closed - Opened by Sanchit-kumar over 1 year ago
#380 - Chapter 7 bootcamp
Pull Request -
State: closed - Opened by quekyj over 1 year ago
#379 - Add `PairInterface`
Pull Request -
State: closed - Opened by mkorbel1 over 1 year ago
#378 - Support a partial assignment `Conditional`
Issue -
State: open - Opened by mkorbel1 over 1 year ago
Labels: enhancement
#377 - Write part-assign automation for `LogicArray`s
Issue -
State: open - Opened by mkorbel1 over 1 year ago
- 2 comments
Labels: enhancement, good first issue
#376 - Complete testing for unpacked arrays in generated SystemVerilog
Issue -
State: open - Opened by mkorbel1 over 1 year ago
Labels: enhancement
#375 - `LogicStructure` and `LogicArray`
Pull Request -
State: closed - Opened by mkorbel1 over 1 year ago
#374 - Documents in `user_guide` aren't ideal for non-website viewing
Issue -
State: closed - Opened by mkorbel1 over 1 year ago
Labels: bug
#373 - Issue#371 Made LogicValue Comparable
Pull Request -
State: closed - Opened by Sanchit-kumar over 1 year ago
#372 - FSM abstraction have issue on priority condition
Issue -
State: closed - Opened by quekyj over 1 year ago
- 1 comment
Labels: bug, enhancement
#371 - Make `LogicValue` comparable
Issue -
State: closed - Opened by mkorbel1 over 1 year ago
- 1 comment
Labels: enhancement, good first issue
#370 - Check devcontainer in CI
Pull Request -
State: closed - Opened by mkorbel1 over 1 year ago
#369 - Chapter 6 bootcamp
Pull Request -
State: closed - Opened by quekyj over 1 year ago
#368 - Issue#316 Prevent self connecting logic
Pull Request -
State: closed - Opened by Sanchit-kumar almost 2 years ago
#362 - 232 add a mechanism for generating random logic values
Pull Request -
State: closed - Opened by quekyj almost 2 years ago
#361 - Issue:#337 Added clog2
Pull Request -
State: closed - Opened by Sanchit-kumar almost 2 years ago
#360 - Add absolute
Issue -
State: closed - Opened by mkorbel1 almost 2 years ago
- 1 comment
Labels: enhancement, good first issue
#359 - Website / user-guide
Pull Request -
State: closed - Opened by quekyj almost 2 years ago
#358 - Chapter 5 bootcamp tutorial
Pull Request -
State: closed - Opened by quekyj almost 2 years ago
#357 - Issue#334: Added enable signal to flipflop
Pull Request -
State: closed - Opened by Sanchit-kumar almost 2 years ago
#356 - Issue #336: Added power functionality
Pull Request -
State: closed - Opened by Sanchit-kumar almost 2 years ago
- 2 comments
#352 - Simulation performance improvements for conditional assignments
Pull Request -
State: closed - Opened by mkorbel1 almost 2 years ago
#351 - Issue#140: Added gt and gte for for consistency to Logic
Pull Request -
State: closed - Opened by Sanchit-kumar almost 2 years ago
#350 - Fix #148: Implemented neq
Pull Request -
State: closed - Opened by Sanchit-kumar almost 2 years ago
#349 - Fix #348: make `Case` and `CaseZ` use edge-sampled signals for expression evaluation
Pull Request -
State: closed - Opened by mkorbel1 almost 2 years ago
#348 - `Case` and `CaseZ` don't use the edge-sampled version of `expression`
Issue -
State: closed - Opened by mkorbel1 almost 2 years ago
Labels: bug
#347 - Optimize `Set`s, `Map`s, and `Module.input`/`output` `get`ters
Pull Request -
State: closed - Opened by mkorbel1 almost 2 years ago
#346 - Optimize `guard` subscription performance in `Combinational`
Pull Request -
State: closed - Opened by mkorbel1 almost 2 years ago