Ecosyste.ms: Issues

An open API service for providing issue and pull request metadata for open source projects.

GitHub / hriener/lorina issues and pull requests

#86 - Fix compilation errors with newer {fmt} versions

Pull Request - State: open - Opened by marcelwa 8 months ago - 1 comment

#85 - CMake stepup for installation

Issue - State: open - Opened by thedrbubba over 1 year ago

#84 - Getting parse errors when reading Verilog files using Lorina Verilog reader

Issue - State: closed - Opened by Maya7991 over 1 year ago - 2 comments

#83 - Script to rstrip files.

Pull Request - State: closed - Opened by hriener over 1 year ago

#82 - Script to rstrip files.

Pull Request - State: closed - Opened by hriener over 1 year ago

#81 - Fix trailing whitespaces at different locations

Pull Request - State: open - Opened by ssmolov over 1 year ago - 4 comments

#80 - Update CIs

Pull Request - State: closed - Opened by hriener over 1 year ago - 1 comment

#79 - Remove trailing whitespaces

Pull Request - State: closed - Opened by ssmolov over 1 year ago - 7 comments

#78 - verilog_parser: support for block /* comments */

Pull Request - State: closed - Opened by kammoh almost 2 years ago - 3 comments

#77 - Supporting 2-to-1 mux in Verilog

Pull Request - State: closed - Opened by lee30sonia about 2 years ago - 1 comment

#76 - [Verilog] Multi-output module instances are instantiated multiple times

Issue - State: closed - Opened by lee30sonia over 2 years ago - 1 comment
Labels: enhancement

#75 - InfInt

Pull Request - State: closed - Opened by hriener almost 3 years ago

#74 - Missing header fix

Pull Request - State: closed - Opened by hriener almost 3 years ago

#73 - Bench File Reading Error

Issue - State: closed - Opened by utdael almost 3 years ago - 4 comments

#72 - verilog to aig

Issue - State: closed - Opened by shi27feng almost 3 years ago - 2 comments

#71 - AST Visitor

Pull Request - State: closed - Opened by hriener almost 3 years ago - 1 comment

#70 - Verilog parser

Pull Request - State: closed - Opened by hriener almost 3 years ago - 1 comment

#69 - windows action.

Pull Request - State: closed - Opened by hriener almost 3 years ago - 1 comment

#68 - Verilog lexer

Pull Request - State: closed - Opened by hriener almost 3 years ago - 1 comment

#67 - Make the DIMACS clause regex more robust

Pull Request - State: closed - Opened by runekrauss about 3 years ago - 4 comments

#66 - Separate signatures when calling in topological order

Pull Request - State: closed - Opened by lee30sonia about 3 years ago - 1 comment

#65 - Tolerate non-topologically ordered module instantiation

Pull Request - State: closed - Opened by lee30sonia over 3 years ago - 1 comment

#64 - Docs update

Pull Request - State: closed - Opened by aletempiac over 3 years ago

#63 - Update Catch2

Pull Request - State: closed - Opened by lee30sonia over 3 years ago - 1 comment

#62 - Add SUPER reader

Pull Request - State: closed - Opened by aletempiac over 3 years ago - 1 comment

#60 - verilog: check if PIN names match when instantiating a module.

Pull Request - State: closed - Opened by hriener over 3 years ago - 1 comment

#59 - Verilog: support for more flexible module instantiation.

Pull Request - State: closed - Opened by hriener over 3 years ago - 1 comment

#58 - Update CI

Pull Request - State: closed - Opened by hriener over 3 years ago - 1 comment

#57 - Reading and writing Verilog with module instantiation

Pull Request - State: closed - Opened by lee30sonia over 3 years ago - 1 comment

#56 - diagnostics engine.

Pull Request - State: closed - Opened by hriener almost 4 years ago - 1 comment

#55 - [[nodiscard]] reader functions.

Pull Request - State: closed - Opened by hriener almost 4 years ago

#54 - diagnostics: improve test coverage.

Pull Request - State: closed - Opened by hriener almost 4 years ago

#53 - DIMACS: improved test coverage.

Pull Request - State: closed - Opened by hriener almost 4 years ago

#52 - .github: CodeCov

Pull Request - State: closed - Opened by hriener almost 4 years ago - 1 comment

#51 - genlib: support for PIN specifications.

Pull Request - State: closed - Opened by hriener almost 4 years ago

#50 - Silence warnings in bristol

Pull Request - State: closed - Opened by lee30sonia almost 4 years ago - 1 comment

#49 - Update author names

Pull Request - State: closed - Opened by hriener almost 4 years ago

#48 - missing header.

Pull Request - State: closed - Opened by hriener almost 4 years ago

#47 - Windows bug

Pull Request - State: closed - Opened by hriener almost 4 years ago

#46 - verilog: test case for parameter definitions.

Pull Request - State: closed - Opened by hriener almost 4 years ago

#45 - SMT-LIB2

Pull Request - State: open - Opened by hriener almost 4 years ago

#44 - Coverage

Pull Request - State: closed - Opened by hriener almost 4 years ago

#43 - Python script to update headers

Pull Request - State: closed - Opened by hriener almost 4 years ago

#42 - GENLIB

Pull Request - State: closed - Opened by hriener almost 4 years ago

#41 - BRISTOL and DIMACS documentation

Pull Request - State: closed - Opened by hriener almost 4 years ago

#40 - ifstream-related updates

Pull Request - State: closed - Opened by lee30sonia almost 4 years ago - 1 comment

#39 - Add DIMACS parser.

Pull Request - State: closed - Opened by boschmitt almost 4 years ago - 1 comment

#38 - Declare individual elements of input registers as known

Pull Request - State: closed - Opened by msoeken almost 5 years ago - 1 comment

#37 - Avoid endless loop in Windows

Pull Request - State: closed - Opened by msoeken almost 5 years ago - 3 comments

#36 - New framework for Aiger tests

Pull Request - State: closed - Opened by hriener almost 5 years ago

#35 - Github action

Pull Request - State: closed - Opened by hriener almost 5 years ago

#34 - mismatch in parsing symbol table of AIG ASCII format?

Issue - State: closed - Opened by mfernan2 almost 5 years ago - 4 comments

#33 - Add missing includes

Pull Request - State: closed - Opened by msoeken almost 5 years ago - 3 comments

#32 - Bristol fashion format

Pull Request - State: closed - Opened by hriener almost 5 years ago

#31 - Integration with the conan package manager

Issue - State: closed - Opened by ruanformigoni almost 5 years ago - 4 comments

#30 - Conan integration

Pull Request - State: closed - Opened by ruanformigoni almost 5 years ago

#29 - operator== on truth tables?

Issue - State: closed - Opened by mfernan2 almost 5 years ago - 3 comments

#28 - blif_reader for sequential `.latch` keyword

Pull Request - State: closed - Opened by hriener almost 5 years ago - 1 comment

#27 - Aiger reader: test latch initialisation.

Pull Request - State: closed - Opened by hriener over 5 years ago - 1 comment

#26 - Aiger reader: indices tests.

Pull Request - State: closed - Opened by hriener over 5 years ago

#25 - some small bugs

Pull Request - State: closed - Opened by fpeng1985 over 5 years ago - 2 comments

#24 - bench: support for DFFs.

Pull Request - State: closed - Opened by hriener over 5 years ago

#22 - Report unresolved dependencies when reading BLIF

Pull Request - State: closed - Opened by hriener over 5 years ago

#21 - topological sorting in `read_blif`.

Pull Request - State: closed - Opened by hriener over 5 years ago

#20 - Extended Verilog format

Pull Request - State: closed - Opened by hriener over 5 years ago

#19 - More fine-grained control for I/O and wire names in Verilog writer

Pull Request - State: closed - Opened by msoeken over 5 years ago - 4 comments

#18 - travis.

Pull Request - State: closed - Opened by hriener over 5 years ago

#17 - bugfix: read-the-docs.

Pull Request - State: closed - Opened by hriener over 5 years ago

#16 - Verilog

Pull Request - State: closed - Opened by hriener almost 6 years ago

#15 - Coverage

Pull Request - State: closed - Opened by hriener almost 6 years ago

#14 - Verilog writer

Pull Request - State: closed - Opened by hriener almost 6 years ago

#13 - Add <vector> to files

Issue - State: closed - Opened by msoeken almost 6 years ago - 1 comment

#12 - Coverage

Pull Request - State: closed - Opened by hriener about 6 years ago

#11 - updating fmt to version 5.2.2

Pull Request - State: closed - Opened by gian21391 over 6 years ago - 3 comments

#10 - Conditional library dependencies

Pull Request - State: closed - Opened by hriener over 6 years ago

#9 - Docs

Pull Request - State: closed - Opened by hriener over 6 years ago

#8 - Topological sorted Verilog.

Pull Request - State: closed - Opened by hriener over 6 years ago

#7 - Ternary operations in Verilog

Pull Request - State: closed - Opened by msoeken over 6 years ago - 1 comment

#6 - Build in Windows

Pull Request - State: closed - Opened by msoeken over 6 years ago - 1 comment

#5 - Wrong include filename

Issue - State: closed - Opened by msoeken over 6 years ago - 1 comment

#4 - Compile error in clang 6.0.0

Issue - State: closed - Opened by msoeken almost 7 years ago - 2 comments

#3 - Fix

Pull Request - State: closed - Opened by gian21391 almost 7 years ago - 2 comments

#2 - EPFL logic synthesis libraries.

Pull Request - State: closed - Opened by msoeken almost 7 years ago - 1 comment

#1 - Trim after splitting.

Pull Request - State: closed - Opened by msoeken almost 7 years ago - 1 comment