Ecosyste.ms: Issues
An open API service for providing issue and pull request metadata for open source projects.
GitHub / google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu7t5v0 issues and pull requests
#30 - Technology LEF files have incorrect CPERSQDIST
Issue -
State: open - Opened by RTimothyEdwards almost 2 years ago
- 15 comments
#29 - wrap unwrapped attributes of test_cell of `ff(IQ1,IQN1)` in quotations
Pull Request -
State: closed - Opened by kareefardi almost 2 years ago
- 5 comments
#28 - liberty issues with yosys
Issue -
State: closed - Opened by kareefardi almost 2 years ago
#27 - Adding missing user defined primitives.
Pull Request -
State: closed - Opened by mithro almost 2 years ago
- 4 comments
#26 - cells: rename functional module
Pull Request -
State: open - Opened by proppy almost 2 years ago
- 10 comments
#25 - .spice netlist is messed up due to label placement
Issue -
State: open - Opened by andylithia almost 2 years ago
- 1 comment
#24 - Gate level verilog modules are horribly broken and unusable
Issue -
State: open - Opened by RTimothyEdwards almost 2 years ago
- 16 comments
#23 - gf180mcu_fd_sc_mcu7t5v0_mux2_1 is seemingly not DRC clean
Issue -
State: closed - Opened by gatecat almost 2 years ago
- 8 comments
#22 - Fixes buffer resizing for PnR tools
Pull Request -
State: closed - Opened by QuantamHD almost 2 years ago
- 6 comments
#21 - tech: move SITE after UNITS
Pull Request -
State: closed - Opened by proppy about 2 years ago
- 1 comment
#20 - tech: add site definition
Pull Request -
State: closed - Opened by proppy about 2 years ago
#19 - Missing Resistance for vias in tech lef
Issue -
State: open - Opened by kareefardi about 2 years ago
- 14 comments
#18 - Missing SITE definition
Issue -
State: closed - Opened by kareefardi about 2 years ago
- 3 comments
Labels: bug
#17 - Rename `METAL1` to `Metal1` in all cells `lef` to match the `techlef`
Pull Request -
State: closed - Opened by kareefardi about 2 years ago
- 3 comments
#16 - Miss-match in metal layer names between cells lef and tech lef
Issue -
State: closed - Opened by kareefardi about 2 years ago
#15 - Fix liberty header names
Pull Request -
State: closed - Opened by RTimothyEdwards about 2 years ago
#14 - Added missing liberty file headers.
Pull Request -
State: closed - Opened by RTimothyEdwards about 2 years ago
- 1 comment
#13 - Set up readthedocs pull request rendering
Issue -
State: open - Opened by mithro about 2 years ago
- 1 comment
#12 - Figure out what is going on with the fill schematic rendering
Issue -
State: open - Opened by mithro about 2 years ago
#11 - Figure out how to fix the flip flop schematic rendering
Issue -
State: open - Opened by mithro about 2 years ago
#10 - Figure out how to fix the buffers schematic rendering
Issue -
State: open - Opened by mithro about 2 years ago
#9 - Fix broken standard cell schematic images
Pull Request -
State: closed - Opened by mohanad0mohamed about 2 years ago
- 1 comment
#8 - Fixing warnings
Pull Request -
State: closed - Opened by mohanad0mohamed about 2 years ago
- 2 comments
#7 - Updating prim names
Pull Request -
State: closed - Opened by FaragElsayed2 about 2 years ago
- 4 comments
#6 - Adding definition.json files
Pull Request -
State: closed - Opened by mohanad0mohamed about 2 years ago
- 3 comments
#5 - Move documentation from base gf180mcu-pdk
Pull Request -
State: closed - Opened by mithro about 2 years ago
- 1 comment
#4 - Add verilog test benches for each of the standard cells.
Issue -
State: open - Opened by mithro about 2 years ago
#3 - Add missing definition.json files for each standard cell
Issue -
State: closed - Opened by mithro about 2 years ago
#2 - CI should check that the standard cells pass the GF180MCU DRC rules
Issue -
State: open - Opened by mithro about 2 years ago
#1 - Get the foss-eda-tools.googlesource.com mirror happening
Issue -
State: closed - Opened by mithro about 2 years ago
- 1 comment