Ecosyste.ms: Issues
An open API service for providing issue and pull request metadata for open source projects.
GitHub / esynr3z/corsair issues and pull requests
#67 - Bugfix Verilog header template
Pull Request -
State: open - Opened by benjjuk 24 days ago
#66 - Support for parametrized unpacked arrays
Issue -
State: open - Opened by g-lesssard 24 days ago
#65 - Register waccess
Pull Request -
State: open - Opened by jrobrien about 2 months ago
#64 - Allow source only installations
Pull Request -
State: open - Opened by martijnbastiaan 2 months ago
#63 - #enhancement : Change rst signal according to _neg / _pos
Issue -
State: open - Opened by stdefeber 3 months ago
#62 - #enhancement : Add wishbone B4 or AHB interface
Issue -
State: open - Opened by stdefeber 3 months ago
#61 - #enhancement : add wishbone b3
Issue -
State: open - Opened by stdefeber 3 months ago
- 3 comments
#60 - Avalon master read fails
Issue -
State: open - Opened by stdefeber 3 months ago
#59 - Verilog waccess not aligned with output data
Issue -
State: open - Opened by sinill57 6 months ago
#58 - Verilog build failed when using multistring description #bug
Issue -
State: open - Opened by iDoka 7 months ago
#57 - Docs update for PR#55 PR#56
Pull Request -
State: open - Opened by iDoka 7 months ago
- 2 comments
#56 - Add verilog template name
Pull Request -
State: open - Opened by iDoka 7 months ago
- 1 comment
#55 - Add asciidoc template name support
Pull Request -
State: open - Opened by iDoka 7 months ago
- 1 comment
#54 - Added option that will add a table to the documentation with an overview of all of the parameters that have a lock indicator
Pull Request -
State: open - Opened by willemss 7 months ago
- 1 comment
#53 - Fixed error when defining a reserved field at LSB position in Markdown template
Pull Request -
State: open - Opened by malsheimer 11 months ago
#52 - c-headers: struct and bit field layout are implementation defined...
Issue -
State: open - Opened by v0lker over 1 year ago
#51 - allow the base address to be a string
Pull Request -
State: open - Opened by v0lker over 1 year ago
#50 - feature request: support symbolic constants for `base_address`, (do not require it to be a number)
Issue -
State: open - Opened by v0lker over 1 year ago
- 1 comment
#49 - Constants and expressions support
Issue -
State: open - Opened by m-kru over 1 year ago
#48 - Addressing mode support
Issue -
State: open - Opened by m-kru over 1 year ago
#47 - Enumeration types support
Issue -
State: open - Opened by m-kru over 1 year ago
#46 - Interrupt support
Issue -
State: open - Opened by m-kru over 1 year ago
#45 - changed PSLVERR output to low (OKAY) in APB2LB template
Pull Request -
State: closed - Opened by malsheimer over 1 year ago
- 1 comment
#44 - Fixed an error that occurred in the HDL (Verilog/VHDL) templates when bit fields are defined such that it results in a 1 bit wide 'reserved' field at position MSB.
Pull Request -
State: closed - Opened by malsheimer over 1 year ago
- 2 comments
#43 - Updated Class Wavedrom() in generators.py
Pull Request -
State: closed - Opened by malsheimer over 1 year ago
#42 - Cam ad
Pull Request -
State: closed - Opened by malsheimer over 1 year ago
#41 - Updated class Wavedrom() in generators.py
Pull Request -
State: closed - Opened by malsheimer over 1 year ago
#40 - New patch v1.0.4
Pull Request -
State: closed - Opened by arnfol over 1 year ago
#39 - Memory interface support
Issue -
State: open - Opened by arnfol over 1 year ago
Labels: enhancement
#38 - Acess mode 'roc' can miss a latch
Issue -
State: open - Opened by arnfol over 1 year ago
Labels: bug
#37 - Fix/rolh miss (issue #28)
Pull Request -
State: closed - Opened by arnfol over 1 year ago
#36 - fix actions
Pull Request -
State: closed - Opened by arnfol over 1 year ago
#35 - bump version
Pull Request -
State: closed - Opened by arnfol over 1 year ago
#34 - Fix vhdl addr constants #33
Pull Request -
State: closed - Opened by arnfol over 1 year ago
Labels: bug
#33 - VHDL target: compare parametric address to constants
Issue -
State: closed - Opened by arnfol over 1 year ago
- 1 comment
Labels: bug
#32 - Queue read not working when FIFO is ready in advance
Issue -
State: closed - Opened by arnfol over 1 year ago
- 2 comments
Labels: bug, duplicate
#31 - base_address for RTL modules
Issue -
State: closed - Opened by vborchsh almost 2 years ago
- 2 comments
#30 - Fix/vhdl tests (copy of #21)
Pull Request -
State: closed - Opened by arnfol almost 2 years ago
Labels: bug, duplicate
#29 - A write-only register with Hardware 'access' option, uses a undeclared *_rdaccess signal
Issue -
State: closed - Opened by nmmalipes almost 2 years ago
- 1 comment
Labels: duplicate
#28 - Access mode 'rolh' can miss a latch
Issue -
State: closed - Opened by nmmalipes almost 2 years ago
- 2 comments
Labels: bug
#27 - #4: verilog/VHDL: only generate access signal for specified access mode
Pull Request -
State: closed - Opened by v0lker about 2 years ago
Labels: bug
#26 - multiple issues in C header generation (padding, masks)
Pull Request -
State: closed - Opened by v0lker about 2 years ago
- 2 comments
Labels: bug
#25 - bugs in c header generation
Issue -
State: closed - Opened by v0lker about 2 years ago
- 3 comments
Labels: bug
#24 - Optional timeout on reads and writes
Issue -
State: open - Opened by stridge-cruxml about 2 years ago
Labels: enhancement
#23 - Move access and hardware from bitfields to reg
Issue -
State: closed - Opened by stridge-cruxml about 2 years ago
- 2 comments
#22 - Added argument to generators to allow passing in of custom template.
Pull Request -
State: open - Opened by stridge-cruxml about 2 years ago
- 1 comment
Labels: enhancement
#21 - Fix/vhdl tests
Pull Request -
State: closed - Opened by stridge-cruxml about 2 years ago
- 2 comments
Labels: bug
#20 - Resolve timescale issues
Issue -
State: closed - Opened by stridge-cruxml about 2 years ago
Labels: bug
#19 - fix: Reading external register with 0 latency
Pull Request -
State: closed - Opened by Xtyll over 2 years ago
- 1 comment
Labels: bug
#18 - Add generator for CMSIS SVD
Pull Request -
State: open - Opened by raffi-g over 2 years ago
Labels: enhancement
#17 - Add generator for CMSIS SVD
Pull Request -
State: closed - Opened by raffi-g over 2 years ago
#16 - Confusing terminology: MSB & LSB vs Offset & Width
Issue -
State: open - Opened by iDoka over 2 years ago
Labels: documentation
#15 - #enhancement: wavedrom bitfield adding `lanes` to csrconfig
Issue -
State: open - Opened by iDoka over 2 years ago
- 2 comments
Labels: documentation, enhancement
#14 - #enhancement: add gitignore which included all auto-generated files
Issue -
State: open - Opened by iDoka over 2 years ago
Labels: enhancement
#13 - #enhancement: add informative header to all auto-generated files
Issue -
State: open - Opened by iDoka over 2 years ago
Labels: enhancement, good first issue
#12 - CMSIS SVD
Issue -
State: open - Opened by raffi-g over 2 years ago
- 2 comments
Labels: enhancement
#11 - Add generator for reStructuredText
Pull Request -
State: open - Opened by raffi-g over 2 years ago
Labels: enhancement
#10 - Fix bugs in c header
Pull Request -
State: closed - Opened by raffi-g over 2 years ago
- 1 comment
Labels: bug
#9 - Fix struct reserved bitwidth spacing in c_template.
Pull Request -
State: closed - Opened by stridge-cruxml over 2 years ago
- 1 comment
#8 - AXI BResp and RResp
Issue -
State: open - Opened by stridge-cruxml over 2 years ago
- 5 comments
Labels: enhancement
#7 - Verilog AXI read queue for first word fall through fifo.
Issue -
State: closed - Opened by stridge-cruxml over 2 years ago
- 2 comments
Labels: bug
#6 - Fix typo in assertion string.
Pull Request -
State: closed - Opened by stridge-cruxml over 2 years ago
#5 - add disclaimer about "wo" access mode
Pull Request -
State: closed - Opened by arnfol over 2 years ago
#4 - Minor bug in VHDL file generation (csr_*_ren signal)
Issue -
State: closed - Opened by arnfol over 2 years ago
- 7 comments
Labels: bug
#3 - feature/spi2lb
Pull Request -
State: closed - Opened by esynr3z over 3 years ago
#2 - New documentation types added
Pull Request -
State: closed - Opened by EgorVorontsov over 3 years ago
- 1 comment
#1 - Avalon-MM added
Pull Request -
State: closed - Opened by evgeniyBolnov over 3 years ago