esynr3z/corsair issues and pull requests

#91 - support RAL generation

Issue - State: open - Opened by roybod about 1 month ago
Labels: kind: feature, new, scope: sw generators

#90 - support xml - ip-xact

Issue - State: open - Opened by roybod about 1 month ago
Labels: kind: feature, new, scope: sw generators

#89 - support bram/fifo interface

Issue - State: open - Opened by roybod about 1 month ago - 4 comments
Labels: kind: feature, scope: hw generators, status: needs discussion

#88 - support register array creation

Issue - State: open - Opened by roybod about 1 month ago - 2 comments
Labels: kind: feature, scope: register map, status: needs discussion

#87 - Bug in c header file

Issue - State: open - Opened by chrisbohens about 1 month ago - 1 comment
Labels: kind: bug, scope: sw generators, status: needs discussion

#86 - Add AHB interface

Issue - State: open - Opened by esynr3z about 2 months ago
Labels: kind: feature, scope: hw generators, status: todo

#85 - Add generator for reStructuredText

Issue - State: open - Opened by esynr3z about 2 months ago
Labels: kind: feature, scope: doc generators, status: todo

#84 - Add option to override csrconfig values via cli

Issue - State: open - Opened by esynr3z about 2 months ago
Labels: kind: feature, scope: cli, status: todo

#83 - Follow "Conventional Commits" specification for the commits

Issue - State: closed - Opened by esynr3z about 2 months ago - 1 comment
Labels: kind: feature, scope: infrastructure, status: done

#82 - Follow "Keep a Changelog" format for the changelog

Issue - State: open - Opened by esynr3z about 2 months ago
Labels: scope: infrastructure, kind: refactoring

#81 - Replace current INI-like configuration file with TOML

Issue - State: open - Opened by esynr3z about 2 months ago
Labels: kind: feature, scope: cli

#80 - Replace LocalBus with APB as a default interface to register map

Issue - State: open - Opened by esynr3z about 2 months ago
Labels: kind: feature, scope: hw generators

#79 - Integrate logger into codebase

Issue - State: closed - Opened by esynr3z about 2 months ago - 1 comment
Labels: kind: feature, scope: arch, status: done

#78 - Add dry-run mode

Issue - State: open - Opened by esynr3z about 2 months ago
Labels: kind: feature, scope: cli

#77 - Test that any non-HDL output is valid

Issue - State: open - Opened by esynr3z about 2 months ago
Labels: kind: feature, scope: sw generators, scope: doc generators, scope: tests

#76 - Prove that generated Verilog/VHDL is equivalent

Issue - State: open - Opened by esynr3z about 2 months ago
Labels: kind: feature, scope: hw generators, scope: tests

#75 - Make sure all generated HDL is lint and warning free

Issue - State: open - Opened by esynr3z about 2 months ago
Labels: kind: feature, scope: infrastructure, scope: hw generators

#74 - Use Verilator/GHDL as main simulators

Issue - State: open - Opened by esynr3z about 2 months ago
Labels: kind: feature, scope: infrastructure

#73 - Outline python versions supported

Issue - State: open - Opened by esynr3z about 2 months ago
Labels: kind: feature, scope: infrastructure

#72 - Use cocotb for HDL testing

Issue - State: open - Opened by esynr3z about 2 months ago
Labels: kind: feature, scope: tests

#71 - Use poetry for dependency and venv management

Issue - State: closed - Opened by esynr3z about 2 months ago - 1 comment
Labels: kind: feature, scope: infrastructure, status: done

#70 - Created development branch

Pull Request - State: closed - Opened by stdefeber about 2 months ago

#69 - Expand Project Maintainership/Ownership

Issue - State: closed - Opened by iamjjw about 2 months ago - 8 comments

#68 - Fixed Avavlon reads

Pull Request - State: open - Opened by stdefeber 2 months ago

#67 - Bugfix Verilog header template

Pull Request - State: open - Opened by benjjuk 3 months ago

#66 - Support for parametrized unpacked arrays

Issue - State: open - Opened by g-lesssard 3 months ago - 1 comment
Labels: kind: feature, scope: register map, status: todo

#65 - Register waccess

Pull Request - State: open - Opened by jrobrien 4 months ago

#64 - Allow source only installations

Pull Request - State: open - Opened by martijnbastiaan 4 months ago

#63 - Change rst signal according to _neg / _pos

Issue - State: open - Opened by stdefeber 5 months ago - 1 comment
Labels: kind: refactoring, scope: hw generators, status: todo

#62 - Add wishbone B4 interface

Issue - State: open - Opened by stdefeber 5 months ago
Labels: kind: feature, scope: hw generators, status: todo

#61 - Add wishbone b3

Issue - State: open - Opened by stdefeber 5 months ago - 3 comments
Labels: kind: feature, scope: hw generators, status: todo

#60 - Avalon master read fails

Issue - State: open - Opened by stdefeber 5 months ago - 1 comment
Labels: kind: bug, scope: hw generators, status: todo

#59 - Verilog waccess not aligned with output data

Issue - State: open - Opened by sinill57 8 months ago - 1 comment
Labels: kind: feature, scope: register map, scope: hw generators, status: needs discussion

#58 - Verilog build failed when using multistring description

Issue - State: open - Opened by iDoka 9 months ago - 1 comment
Labels: kind: bug, scope: register map, status: needs discussion

#57 - Docs update for PR#55 PR#56

Pull Request - State: open - Opened by iDoka 9 months ago - 2 comments

#56 - Add verilog template name

Pull Request - State: open - Opened by iDoka 9 months ago - 1 comment

#55 - Add asciidoc template name support

Pull Request - State: open - Opened by iDoka 9 months ago - 1 comment

#54 - Added option that will add a table to the documentation with an overview of all of the parameters that have a lock indicator

Pull Request - State: open - Opened by willemss 9 months ago - 1 comment

#53 - Fixed error when defining a reserved field at LSB position in Markdown template

Pull Request - State: open - Opened by malsheimer about 1 year ago

#52 - c-headers: struct and bit field layout are implementation defined...

Issue - State: open - Opened by v0lker over 1 year ago - 1 comment
Labels: kind: feature, scope: sw generators, status: needs discussion

#51 - allow the base address to be a string

Pull Request - State: closed - Opened by v0lker over 1 year ago - 1 comment

#50 - feature request: support symbolic constants for `base_address`, (do not require it to be a number)

Issue - State: open - Opened by v0lker over 1 year ago - 2 comments
Labels: kind: feature, scope: cli, scope: sw generators, status: needs discussion

#49 - Constants and expressions support

Issue - State: open - Opened by m-kru over 1 year ago - 1 comment
Labels: kind: feature, status: needs discussion

#48 - Addressing mode support

Issue - State: open - Opened by m-kru over 1 year ago - 1 comment
Labels: kind: feature, scope: register map, status: needs discussion

#47 - Enumeration types support

Issue - State: open - Opened by m-kru over 1 year ago - 1 comment
Labels: kind: feature, scope: register map, status: needs discussion

#46 - Interrupt support

Issue - State: open - Opened by m-kru over 1 year ago - 1 comment
Labels: kind: feature, status: needs discussion

#45 - changed PSLVERR output to low (OKAY) in APB2LB template

Pull Request - State: closed - Opened by malsheimer over 1 year ago - 1 comment

#44 - Fixed an error that occurred in the HDL (Verilog/VHDL) templates when bit fields are defined such that it results in a 1 bit wide 'reserved' field at position MSB.

Pull Request - State: closed - Opened by malsheimer over 1 year ago - 2 comments

#43 - Updated Class Wavedrom() in generators.py

Pull Request - State: closed - Opened by malsheimer over 1 year ago

#42 - Cam ad

Pull Request - State: closed - Opened by malsheimer over 1 year ago

#41 - Updated class Wavedrom() in generators.py

Pull Request - State: closed - Opened by malsheimer over 1 year ago

#40 - New patch v1.0.4

Pull Request - State: closed - Opened by arnfol over 1 year ago

#39 - Memory interface support

Issue - State: open - Opened by arnfol over 1 year ago - 1 comment
Labels: kind: feature, scope: register map, status: todo

#38 - Acess mode 'roc' can miss a latch

Issue - State: open - Opened by arnfol over 1 year ago - 1 comment
Labels: kind: bug, scope: register map, scope: hw generators, status: needs discussion

#37 - Fix/rolh miss (issue #28)

Pull Request - State: closed - Opened by arnfol over 1 year ago

#36 - fix actions

Pull Request - State: closed - Opened by arnfol over 1 year ago

#35 - bump version

Pull Request - State: closed - Opened by arnfol over 1 year ago

#34 - Fix vhdl addr constants #33

Pull Request - State: closed - Opened by arnfol over 1 year ago
Labels: bug

#33 - VHDL target: compare parametric address to constants

Issue - State: closed - Opened by arnfol over 1 year ago - 1 comment
Labels: bug

#32 - Queue read not working when FIFO is ready in advance

Issue - State: closed - Opened by arnfol over 1 year ago - 2 comments
Labels: bug, duplicate

#31 - base_address for RTL modules

Issue - State: closed - Opened by vborchsh almost 2 years ago - 2 comments

#30 - Fix/vhdl tests (copy of #21)

Pull Request - State: closed - Opened by arnfol about 2 years ago
Labels: bug, duplicate

#29 - A write-only register with Hardware 'access' option, uses a undeclared *_rdaccess signal

Issue - State: closed - Opened by nmmalipes about 2 years ago - 1 comment
Labels: duplicate

#28 - Access mode 'rolh' can miss a latch

Issue - State: closed - Opened by nmmalipes about 2 years ago - 2 comments
Labels: bug

#27 - #4: verilog/VHDL: only generate access signal for specified access mode

Pull Request - State: closed - Opened by v0lker about 2 years ago
Labels: bug

#26 - multiple issues in C header generation (padding, masks)

Pull Request - State: closed - Opened by v0lker about 2 years ago - 2 comments
Labels: bug

#25 - bugs in c header generation

Issue - State: closed - Opened by v0lker about 2 years ago - 3 comments
Labels: bug

#24 - Optional timeout on reads and writes

Issue - State: open - Opened by stridge-cruxml over 2 years ago - 1 comment
Labels: kind: feature, scope: hw generators, status: needs discussion

#23 - Move access and hardware from bitfields to reg

Issue - State: closed - Opened by stridge-cruxml over 2 years ago - 2 comments

#22 - Added argument to generators to allow passing in of custom template.

Pull Request - State: open - Opened by stridge-cruxml over 2 years ago - 1 comment
Labels: enhancement

#21 - Fix/vhdl tests

Pull Request - State: closed - Opened by stridge-cruxml over 2 years ago - 2 comments
Labels: bug

#20 - Resolve timescale issues

Issue - State: closed - Opened by stridge-cruxml over 2 years ago
Labels: bug

#19 - fix: Reading external register with 0 latency

Pull Request - State: closed - Opened by Xtyll over 2 years ago - 1 comment
Labels: bug

#18 - Add generator for CMSIS SVD

Pull Request - State: open - Opened by raffi-g over 2 years ago
Labels: enhancement

#17 - Add generator for CMSIS SVD

Pull Request - State: closed - Opened by raffi-g over 2 years ago

#16 - Confusing terminology: MSB & LSB vs Offset & Width

Issue - State: open - Opened by iDoka over 2 years ago - 1 comment
Labels: scope: register map, kind: refactoring, status: todo

#15 - Wavedrom bitfield adding `lanes` to csrconfig

Issue - State: open - Opened by iDoka over 2 years ago - 3 comments
Labels: kind: feature, scope: doc generators, status: todo

#14 - Add gitignore which included all auto-generated files

Issue - State: open - Opened by iDoka over 2 years ago - 1 comment
Labels: scope: infrastructure, status: todo

#13 - Add informative header to all auto-generated files

Issue - State: open - Opened by iDoka over 2 years ago - 1 comment
Labels: scope: documentation, kind: refactoring, scope: hw generators, scope: doc generators, status: todo

#12 - Add generator for CMSIS SVD

Issue - State: open - Opened by raffi-g over 2 years ago - 3 comments
Labels: kind: feature, scope: sw generators, status: todo

#11 - Add generator for reStructuredText

Pull Request - State: open - Opened by raffi-g over 2 years ago
Labels: enhancement

#10 - Fix bugs in c header

Pull Request - State: closed - Opened by raffi-g over 2 years ago - 1 comment
Labels: bug

#9 - Fix struct reserved bitwidth spacing in c_template.

Pull Request - State: closed - Opened by stridge-cruxml over 2 years ago - 1 comment

#8 - Return explicit error on access violations

Issue - State: open - Opened by stridge-cruxml over 2 years ago - 6 comments
Labels: kind: feature, scope: hw generators, status: todo

#7 - Verilog AXI read queue for first word fall through fifo.

Issue - State: closed - Opened by stridge-cruxml over 2 years ago - 2 comments
Labels: bug

#6 - Fix typo in assertion string.

Pull Request - State: closed - Opened by stridge-cruxml over 2 years ago

#5 - add disclaimer about "wo" access mode

Pull Request - State: closed - Opened by arnfol almost 3 years ago

#4 - Minor bug in VHDL file generation (csr_*_ren signal)

Issue - State: closed - Opened by arnfol almost 3 years ago - 7 comments
Labels: bug

#3 - feature/spi2lb

Pull Request - State: closed - Opened by esynr3z over 3 years ago

#2 - New documentation types added

Pull Request - State: closed - Opened by EgorVorontsov over 3 years ago - 1 comment

#1 - Avalon-MM added

Pull Request - State: closed - Opened by evgeniyBolnov almost 4 years ago

GitHub / esynr3z/corsair issues and pull requests