enjoy-digital/litex issues and pull requests

#2187 - Fix issue enjoy-digital#2182

Pull Request - State: closed - Opened by benjaminh-13 2 days ago - 1 comment

#2186 - Use Python's raw string in regex pattern.

Pull Request - State: closed - Opened by higuoxing 3 days ago - 1 comment

#2185 - Optimize memspeed test for cores with slow modulo.

Pull Request - State: closed - Opened by cr1901 3 days ago - 1 comment

#2184 - Error when trying to build base VexRiscV example on Alinx7203 Artix7 Board

Issue - State: open - Opened by tarik-hamedovic 4 days ago

#2183 - Added fujprog in Lattice progammer for ULX3S

Pull Request - State: closed - Opened by tarik-hamedovic 4 days ago - 1 comment

#2182 - Compiling software for 32-bits NaxRiscv SoC fails when forcing xlen=32 through the CLI

Issue - State: closed - Opened by benjaminh-13 5 days ago - 7 comments
Labels: software-bug

#2181 - build/efinix/platform.py: get_pins_name: avoids to create a new signal with a name already existing

Pull Request - State: closed - Opened by trabucayre 6 days ago - 1 comment

#2180 - litex/build/efinix/platform.py: get_pin_name method: always adds idx to the signal name -> avoid some inversion between my_sig and my_sig_1

Pull Request - State: closed - Opened by trabucayre 6 days ago - 1 comment

#2179 - Having comma in ident causes exception in `CSRBuilder`

Issue - State: open - Opened by kaolpr 7 days ago
Labels: software-bug

#2178 - Converting Wishbone to riscv-steel custom bus

Issue - State: open - Opened by BMorgan1296 13 days ago - 1 comment
Labels: question, new-feature

#2177 - Support SD cards in DDR50 mode

Issue - State: open - Opened by machdyne 13 days ago - 1 comment
Labels: enhancement

#2176 - Update migen version to work with python3.13

Pull Request - State: closed - Opened by david-sawatzke 14 days ago - 3 comments

#2175 - litex_setup: Current `--tag` argument does not work

Issue - State: open - Opened by nickyu42 15 days ago - 1 comment
Labels: bug?, answered-waiting-feedback

#2174 - Add support for the Sentinel RISC-V CPU.

Pull Request - State: open - Opened by cr1901 16 days ago - 5 comments

#2173 - ERROR: [DRC PDRC-43] when adding Alinx7203 board in litex-boards

Issue - State: closed - Opened by TarikHamedovic 16 days ago - 2 comments

#2172 - UART output garbled when building Litex SoC for CrossLinkNX with Radiant 2024.2

Issue - State: open - Opened by polymerizedsage 17 days ago - 2 comments
Labels: bug?, regression

#2171 - soc/cores/clock/gowin_gw5a.py: GW5AT uses PLLA

Pull Request - State: closed - Opened by trabucayre 17 days ago - 1 comment

#2170 - Fix NaxRISCV Bare Metal Demo and small fix for demo.py make routine

Pull Request - State: closed - Opened by BMorgan1296 22 days ago - 1 comment

#2169 - NaxRISCV Bare Metal Demo not working

Issue - State: closed - Opened by BMorgan1296 25 days ago - 9 comments

#2168 - build: common: TristateImpl: support longer oe

Pull Request - State: closed - Opened by maass-hamburg 27 days ago - 1 comment

#2167 - build: common: make sure Signal lenght is right

Pull Request - State: closed - Opened by maass-hamburg 28 days ago - 1 comment

#2166 - soc: interconnect: add logic to set a offset to bus slaves

Pull Request - State: open - Opened by maass-hamburg 29 days ago - 3 comments

#2165 - litex: gen: fhdl: verilog.py: resolve slice in lower_complex_slices()

Pull Request - State: closed - Opened by maass-hamburg about 1 month ago - 5 comments

#2164 - Litex last (master) not build project

Issue - State: closed - Opened by faa00 about 1 month ago - 3 comments
Labels: answered-waiting-feedback

#2163 - soc.py: ethernet: use phy_cd name from phy

Pull Request - State: open - Opened by maass-hamburg about 1 month ago - 2 comments

#2162 - build/altera/quartus.py: don't call FullMemoryWE when target is based on max10 FPGA

Pull Request - State: closed - Opened by trabucayre about 1 month ago

#2161 - gen: fhdl: expression: resolve slice completly

Pull Request - State: closed - Opened by maass-hamburg about 1 month ago - 2 comments

#2160 - cores/cpu/ibex: Align with latest RTL

Pull Request - State: closed - Opened by FlyGoat about 1 month ago - 1 comment

#2159 - cores/cpu/openc906: Align with pythondata RTL

Pull Request - State: closed - Opened by FlyGoat about 1 month ago - 1 comment

#2158 - soc/interconnect/wishbone: Add Wishbone CDC

Pull Request - State: open - Opened by david-sawatzke about 1 month ago - 2 comments

#2157 - Linking in libliteeth causes binary to fail to execute

Issue - State: open - Opened by kscz about 1 month ago - 7 comments

#2156 - Please switch from setup-ghdl-ci to setup-ghdl

Issue - State: open - Opened by Paebbels about 1 month ago

#2155 - Problem adding a new CPU

Issue - State: open - Opened by DaviLdM about 1 month ago - 2 comments
Labels: install, third-party-bug, answered-waiting-feedback

#2154 - Add (optional) clock parameter when instantiating xgmii module

Pull Request - State: open - Opened by david-sawatzke about 1 month ago

#2153 - [enh] Added differential input for ICE40

Pull Request - State: closed - Opened by chmousset about 2 months ago - 1 comment

#2152 - Support for Python 3.13

Issue - State: closed - Opened by david-sawatzke about 2 months ago - 1 comment

#2149 - Disabling interrupts in bios for serial boot, re-enabling when files are uploaded completely.

Issue - State: open - Opened by Rajnesh28 about 2 months ago - 1 comment

#2148 - backwards compatibility with python3.7

Pull Request - State: closed - Opened by dayjaby 2 months ago - 1 comment

#2147 - build/gowin/programmer: refactor GowinProgrammer for enhanced functionality

Pull Request - State: closed - Opened by andelf 2 months ago - 1 comment

#2146 - test: Include more bus option tests

Pull Request - State: closed - Opened by FlyGoat 2 months ago - 1 comment

#2145 - build/vhd2v_converter: allows using an instance instead of entity_name + params

Pull Request - State: closed - Opened by trabucayre 2 months ago - 1 comment

#2144 - tests: Improve GitHub CI action

Pull Request - State: open - Opened by FlyGoat 2 months ago - 6 comments

#2143 - soc/integration/soc: Fix CSRBridge Bus Width conversion

Pull Request - State: closed - Opened by FlyGoat 2 months ago - 4 comments

#2142 - Fix WS2812 with nled=1

Pull Request - State: closed - Opened by andelf 2 months ago - 1 comment

#2141 - Combination of --toolchain=openxc7 and --no-compile-gateware options

Issue - State: open - Opened by Mecrisp 2 months ago

#2140 - soc/ethernet: enable full_memory_we by default for Quartus toolchain

Pull Request - State: closed - Opened by piotro888 2 months ago - 4 comments

#2139 - cores/clock/intel: add reset to Intel PLLs

Pull Request - State: closed - Opened by piotro888 2 months ago - 6 comments

#2138 - efinix_trion_t20_mipi_dev_kit SPI flash and litex demo issues

Issue - State: closed - Opened by Kanken6174 2 months ago - 12 comments

#2137 - build/xilinx/platform: added xilinx_us_special_overrides for xczu devices

Pull Request - State: closed - Opened by trabucayre 2 months ago - 1 comment

#2136 - Memory initialization files

Issue - State: open - Opened by merveyubogluu 2 months ago - 3 comments
Labels: answered-waiting-feedback

#2135 - Fix litex_setup.py OHCI clone

Pull Request - State: closed - Opened by Dolu1990 2 months ago - 1 comment

#2134 - Wishbone adapter to access flash through a movable window

Issue - State: open - Opened by NateMeyer 3 months ago - 2 comments
Labels: answered-waiting-feedback

#2133 - Fixed for eliminating picolibc in package writing

Pull Request - State: open - Opened by kaolpr 3 months ago

#2132 - Error while finding module specification for 'litex.soc.software.crcfbigen' (ModuleNotFoundError: No module named 'litex')

Issue - State: closed - Opened by ltapmaracanau 3 months ago

#2131 - liblitespi: fix typo

Pull Request - State: closed - Opened by awaittrot 3 months ago - 1 comment

#2130 - cores/cpu/vexiiriscv: Add PMP support

Pull Request - State: closed - Opened by Dolu1990 3 months ago - 1 comment

#2130 - cores/cpu/vexiiriscv: Add PMP support

Pull Request - State: open - Opened by Dolu1990 3 months ago

#2129 - liblitespi: add 4k erase function

Pull Request - State: open - Opened by m-byte 3 months ago

#2129 - liblitespi: add 4k erase function

Pull Request - State: closed - Opened by m-byte 3 months ago - 1 comment

#2128 - Add efinix SEU interface

Pull Request - State: closed - Opened by m-byte 3 months ago - 1 comment

#2128 - Add efinix SEU interface

Pull Request - State: open - Opened by m-byte 3 months ago

#2127 - Fix vdb path for Efinity 2024.2

Pull Request - State: closed - Opened by m-byte 3 months ago - 1 comment

#2126 - No compatibility with Efinity 2024.2.294

Issue - State: open - Opened by m-byte 3 months ago - 4 comments

#2125 - build/lattice/common.py: added Tristate support for ECP5 when build with diamond

Pull Request - State: closed - Opened by trabucayre 3 months ago - 1 comment

#2124 - SPI "Manual Operation useful for Bulk transfers" seems to do nothing

Issue - State: open - Opened by YusufCelik 3 months ago - 1 comment

#2123 - build/vhd2v_converter.py: allows users to pass a list of libraries files to compile before convert HDL.

Pull Request - State: closed - Opened by trabucayre 3 months ago - 1 comment

#2122 - feat: add uart_with_dynamic_baudrate to SoCCore

Pull Request - State: closed - Opened by jwise 3 months ago

#2121 - CVA6 + Nexys4 DDR - RAM access issues

Issue - State: open - Opened by juanschroeder 3 months ago

#2120 - Fixes: Fix not close trace file when the sim is finished

Pull Request - State: closed - Opened by juiceRv 3 months ago - 2 comments

#2119 - Utilizing all available CPU cores in the software make cmd

Pull Request - State: closed - Opened by long-pham 3 months ago - 1 comment

#2118 - Add FTDI serial number option to openfpgaloader

Pull Request - State: closed - Opened by long-pham 3 months ago - 1 comment

#2117 - Use MMCME4_ADV in USPMMCM to enable finer-grained clock output ctrl

Pull Request - State: closed - Opened by long-pham 3 months ago - 1 comment

#2116 - Add "--depth" and "-b" arguments for git clone command

Pull Request - State: open - Opened by John-Tito 4 months ago

#2115 - Fix SOC region range check

Pull Request - State: closed - Opened by CKeilbar 4 months ago

#2114 - SoC range check boundary issue

Issue - State: closed - Opened by CKeilbar 4 months ago

#2113 - litex/build/lattice/diamond, platform: allows users to add custom sdc files

Pull Request - State: closed - Opened by trabucayre 4 months ago - 1 comment

#2112 - Video-terminal has useable Funtion?

Issue - State: open - Opened by 2jack5657 4 months ago - 1 comment
Labels: question, answered-waiting-feedback

#2111 - Optimize Build, Enhance Clock Control, and add FTDI serial number option to openfpgaloader

Pull Request - State: closed - Opened by long-pham 4 months ago - 2 comments

#2110 - litex_sim hangs when adding a call to a function in libliteeth

Issue - State: open - Opened by jersey99 4 months ago - 2 comments

#2109 - Implementing reset comming from the CPU jtag

Issue - State: open - Opened by Dolu1990 4 months ago

#2108 - Stuck at "liftoff" when I try romboot

Issue - State: open - Opened by Stars-Collector 4 months ago

#2107 - Cant have multiple Instances of Custom VHDL core

Issue - State: open - Opened by Haron123 4 months ago - 1 comment

#2106 - bios: add flash_transfer_cmd

Pull Request - State: open - Opened by cklarhorst 4 months ago

#2105 - build: io: add multibit/bus variants of SDR and DDR

Pull Request - State: closed - Opened by maass-hamburg 4 months ago - 13 comments

#2104 - Fixes #2103: calculate memory depth for WS2812

Pull Request - State: closed - Opened by andelf 4 months ago - 1 comment

#2103 - Unable to create WS2812 of nleds = 1

Issue - State: closed - Opened by andelf 4 months ago

#2102 - Vexiiriscv update

Pull Request - State: closed - Opened by Dolu1990 4 months ago - 1 comment

#2101 - bios: litespi: clear rx queue after write Beta

Pull Request - State: closed - Opened by maass-hamburg 4 months ago - 1 comment

#2100 - efinix: gpio: use constant output option

Pull Request - State: closed - Opened by maass-hamburg 4 months ago - 2 comments

#2099 - vexiiriscv: add options and conditions

Pull Request - State: closed - Opened by maass-hamburg 4 months ago - 5 comments

#2098 - Add initial uRV CPU support.

Pull Request - State: closed - Opened by enjoy-digital 4 months ago

#2097 - Build diamond addition

Pull Request - State: closed - Opened by trabucayre 4 months ago - 1 comment

#2096 - UartLite as a separate module.

Issue - State: open - Opened by mohammadshahidzade 4 months ago - 2 comments

#2095 - soc/cores/cpu/zynqmp/core.py: added support for SGMII via PL with optional PTP support

Pull Request - State: closed - Opened by trabucayre 4 months ago - 1 comment

#2094 - Using irq_setie(1) messes normal programm execution on vexriscv

Issue - State: closed - Opened by Haron123 4 months ago - 1 comment

#2093 - Fixes #2092: provides support for riscv gcc installation on Alpine Linux.

Pull Request - State: closed - Opened by mgaggero 4 months ago - 1 comment

#2092 - litex_setup.py does not install riscv gcc on Alpine Linux

Issue - State: closed - Opened by mgaggero 4 months ago

#2091 - Generated Verilog project can't work

Issue - State: open - Opened by snowprogrammer 4 months ago - 2 comments

#2090 - build: efinix: use ifacewriter to set bank voltage

Pull Request - State: closed - Opened by maass-hamburg 4 months ago - 1 comment

#2089 - build: efinix: Tristate fix

Pull Request - State: closed - Opened by maass-hamburg 5 months ago - 2 comments

GitHub / enjoy-digital/litex issues and pull requests