enjoy-digital/litedram issues and pull requests

#45 - Implement tRAS

Pull Request - State: closed - Opened by JohnSully about 6 years ago - 3 comments

#44 - This adds support for tRC timing parameters

Pull Request - State: closed - Opened by JohnSully about 6 years ago - 1 comment

#43 - Bank valid/ready refactor

Pull Request - State: closed - Opened by JohnSully about 6 years ago - 1 comment

#42 - We wait an extra cycle for no reason

Pull Request - State: closed - Opened by JohnSully about 6 years ago - 2 comments

#41 - TypeError: phase_cmd_description() missing 1 required positional argument: 'nranks'

Issue - State: closed - Opened by mithro about 6 years ago

#40 - 1:2 Sequential Access Throughput is Lower Than Expected

Issue - State: closed - Opened by JohnSully about 6 years ago - 3 comments
Labels: enhancement, help-wanted

#39 - Multirank: add dynamic ODT

Issue - State: open - Opened by enjoy-digital about 6 years ago
Labels: enhancement, help-wanted

#38 - Multirank

Pull Request - State: closed - Opened by enjoy-digital about 6 years ago

#37 - Can't calibrate

Issue - State: closed - Opened by JohnSully about 6 years ago - 3 comments

#36 - Fix failing timing

Pull Request - State: closed - Opened by JohnSully about 6 years ago - 4 comments

#35 - BL8 1:2 hangs with UART bridge

Issue - State: closed - Opened by JohnSully about 6 years ago - 10 comments

#34 - BL8 1:2 controller fails to compile

Issue - State: closed - Opened by JohnSully about 6 years ago - 1 comment

#33 - Add BL8 support for S7DDRPHY in 1:2

Issue - State: closed - Opened by enjoy-digital about 6 years ago - 3 comments

#32 - Verify DDR3 MR0 Write Recovery configuration

Issue - State: closed - Opened by enjoy-digital over 6 years ago - 1 comment
Labels: enhancement, help-wanted

#31 - Verify DDR3 DQS Write Preamble/Postamble

Issue - State: closed - Opened by enjoy-digital over 6 years ago - 1 comment
Labels: enhancement, help-wanted, question

#30 - Add Reordering support

Issue - State: open - Opened by enjoy-digital over 6 years ago - 3 comments
Labels: enhancement, help-wanted

#29 - Allow all CL/CWL combinations to be used with DDR3

Issue - State: closed - Opened by enjoy-digital over 6 years ago - 3 comments
Labels: enhancement, help-wanted

#28 - i think there's a missing "self" in the params

Pull Request - State: closed - Opened by bunnie over 6 years ago - 1 comment

#27 - board tuning parameters added

Pull Request - State: closed - Opened by bunnie over 6 years ago - 2 comments

#26 - Refresh command is not issued.

Issue - State: closed - Opened by JohnSully over 6 years ago - 1 comment

#25 - Multiple Timings Ignored

Issue - State: closed - Opened by JohnSully over 6 years ago - 1 comment

#24 - Auto precharge

Pull Request - State: closed - Opened by JohnSully over 6 years ago - 1 comment

#23 - Out of Order Completion

Pull Request - State: closed - Opened by JohnSully over 6 years ago - 1 comment

#22 - Out of order interface is incomplete

Issue - State: closed - Opened by JohnSully over 6 years ago - 3 comments

#21 - Outoforder

Pull Request - State: closed - Opened by enjoy-digital over 6 years ago

#20 - add 400MHz tap setting (valid for -3 and -2/2E speed grades)

Pull Request - State: closed - Opened by bunnie over 6 years ago - 1 comment

#19 - Fix timing issues (tRRD, tCCD, and tFAW)

Pull Request - State: closed - Opened by JohnSully over 6 years ago - 1 comment

#18 - Add tRRD timing checks, and fix tFAW so it considers all banks

Pull Request - State: closed - Opened by JohnSully over 6 years ago

#17 - tRRD and tFAW not respected

Issue - State: closed - Opened by JohnSully over 6 years ago - 3 comments

#16 - 1:2 Controller hard to meet timing

Issue - State: closed - Opened by JohnSully over 6 years ago - 1 comment

#15 - 1:2 7-series Phy doesn't issue commands in write mode

Issue - State: closed - Opened by JohnSully over 6 years ago - 3 comments

#14 - ddr calibration fails when SoC temperature is hot

Issue - State: closed - Opened by xobs over 6 years ago - 2 comments

#13 - settings.timing.tWTR expressed in nanoseconds but used as cycles

Issue - State: closed - Opened by JohnSully over 6 years ago - 1 comment

#12 - Add auto-precharge support

Pull Request - State: closed - Opened by JohnSully over 6 years ago - 12 comments

#11 - Latest litedram fails on the Digilent Atlys board

Issue - State: closed - Opened by mithro over 6 years ago - 1 comment

#10 - migen

Issue - State: closed - Opened by jrrk over 6 years ago - 1 comment

#9 - Fix all remaining indentation issues in python code

Pull Request - State: closed - Opened by felixheld almost 7 years ago

#8 - Add some information about performance / bandwidth

Issue - State: closed - Opened by mithro over 7 years ago - 2 comments
Labels: enhancement, help-wanted

#7 - Add support for ice40 with sdram (CAT board?)

Issue - State: closed - Opened by mithro over 7 years ago - 2 comments

#6 - Litedram is currently broken on the minispartan6+

Issue - State: closed - Opened by mithro over 7 years ago - 7 comments
Labels: gateware-bug, help-wanted

#5 - Creating a utility module for easily scoping the LiteDRAMBISTChecker module.

Pull Request - State: closed - Opened by mithro almost 8 years ago - 2 comments

#4 - Create utility module for easily scoping LiteDRAMBISTChecker

Pull Request - State: closed - Opened by mithro almost 8 years ago

#3 - Improve the BIST testbench and documentation

Pull Request - State: closed - Opened by mithro almost 8 years ago - 1 comment

#2 - Improvement to the build in self test

Pull Request - State: closed - Opened by mithro almost 8 years ago - 1 comment

#1 - Adding .gitignore file.

Pull Request - State: closed - Opened by mithro over 8 years ago

GitHub / enjoy-digital/litedram issues and pull requests