enjoy-digital/litedram issues and pull requests

#361 - frontend/dma.py: Remove left-over rsv_level documentation

Pull Request - State: open - Opened by david-sawatzke about 1 month ago

#360 - litedram/address_mapping Add bank_byte_alignment

Pull Request - State: closed - Opened by Dolu1990 5 months ago - 1 comment

#359 - modules: add Insignis NDS36PT5

Pull Request - State: closed - Opened by maass-hamburg 6 months ago - 1 comment

#358 - Wishbone, 2 writes followed by colliding read returns incorrect result, write stuck in FIFO

Issue - State: open - Opened by epsilon537 7 months ago - 2 comments
Labels: bug?

#357 - Adding support to gowin phys in litedram.gen?

Issue - State: open - Opened by linhz0hz 7 months ago - 1 comment
Labels: enhancement

#356 - LiteDRAMDMAWriter sinks data when not enabled

Issue - State: open - Opened by DaveBerkeley 7 months ago - 2 comments
Labels: bug?

#355 - Wishbone port does not accept more than one operation despite cmd_buffer_depth non-null in LiteDram yaml file,

Issue - State: open - Opened by fontamsoc 8 months ago
Labels: bug?

#354 - stable avalon frontend

Pull Request - State: closed - Opened by hansfbaier 10 months ago - 1 comment

#353 - GENDDRPHY support?

Issue - State: open - Opened by rhgndf 11 months ago

#352 - litedram/phy/lpddr*: fix use of invalid escape sequence

Pull Request - State: closed - Opened by maribu 11 months ago - 1 comment

#351 - phy/gw5ddrphy: introducing GW5A DDR phy

Pull Request - State: closed - Opened by trabucayre about 1 year ago - 1 comment

#350 - Add W9812G6JB SDRAM module

Pull Request - State: closed - Opened by hansfbaier about 1 year ago - 1 comment

#349 - litedram with vexriscv DDR4 SODIMM fails memtest (Xilinx VU9P + spd)

Issue - State: open - Opened by jersey99 about 1 year ago - 5 comments

#348 - Use bump2version to keep code and tag in sync, small cleanups and enhancements

Pull Request - State: open - Opened by timkpaine about 1 year ago

#347 - DE10-Lite Memory initialization failed

Issue - State: open - Opened by LearnShareAlways about 1 year ago

#346 - Underclocking DRAM controler to increase access time

Issue - State: open - Opened by denishoornaert over 1 year ago

#345 - LiteDRAM core targeting DDR3 issues activate command twice for a write operation

Issue - State: open - Opened by dinaabdelbaky over 1 year ago

#344 - LiteDRAM DDR3 Core targeting Arty AXI read data appears on the Native port instead.

Issue - State: open - Opened by dinaabdelbaky over 1 year ago - 1 comment

#343 - phy/gw2ddrphy: migen.genlib -> litex.gen.genlib (fix commit 6297370e3c)

Pull Request - State: closed - Opened by trabucayre over 1 year ago - 1 comment

#342 - Axi port write data error

Issue - State: open - Opened by Yuxin-Yu over 1 year ago - 8 comments

#341 - add burst converter tests, fix downconverting burst

Pull Request - State: closed - Opened by hansfbaier over 1 year ago - 3 comments

#340 - frontend/avalon: properly implement bursts

Pull Request - State: closed - Opened by hansfbaier over 1 year ago - 35 comments

#339 - Is it possible to adjust burst-length in order to widen data path ?

Issue - State: open - Opened by fontamsoc over 1 year ago

#338 - wb_ctrl ports of ECP5 litedram_core generated for OrangeCrab02-25F failing when user_ports is native

Issue - State: open - Opened by fontamsoc over 1 year ago

#337 - Avalon frontend for LiteDRAM

Pull Request - State: closed - Opened by hansfbaier over 1 year ago - 11 comments

#336 - LiteDRAMDMAWriter cannot write accurate data to a specific address?

Issue - State: open - Opened by Prigana over 1 year ago

#335 - Fix AxSIZE

Pull Request - State: open - Opened by TheZoq2 over 1 year ago

#334 - AxSIZE mismatch?

Issue - State: open - Opened by TheZoq2 over 1 year ago - 1 comment

#333 - Setting for user_clk

Issue - State: open - Opened by ztachip over 1 year ago - 1 comment
Labels: question

#332 - Add support for clam shell topology

Pull Request - State: closed - Opened by jiegec over 1 year ago - 1 comment

#331 - Generate liteDRAM verilog file

Issue - State: closed - Opened by ztachip over 1 year ago - 4 comments

#330 - add manifest, uplift setup.py to pass twine checks

Pull Request - State: closed - Opened by timkpaine over 1 year ago - 1 comment

#329 - ulx3s example does not work

Issue - State: open - Opened by TheZoq2 over 1 year ago - 3 comments
Labels: add-answer-to-wiki

#328 - DDR4 reads without DQS at high speeds?

Issue - State: open - Opened by alexey-morozov almost 2 years ago - 1 comment
Labels: question

#327 - Carrying out the LiteDRAM standalone core initialization manually, through wishbone ctrl interface

Issue - State: open - Opened by dinaabdelbaky almost 2 years ago - 5 comments

#326 - phy/gw2ddrphy: supressing warnings about unconnected and bit length.

Pull Request - State: closed - Opened by trabucayre almost 2 years ago - 1 comment

#325 - --top-module 'sim' was not found in the design

Issue - State: open - Opened by CarrolXC almost 2 years ago - 5 comments
Labels: question

#324 - Need Help Generating Verilog DRAM controller, while maininting module hiraerachies.

Issue - State: closed - Opened by dinaabdelbaky almost 2 years ago - 1 comment
Labels: question

#323 - Mczyz/ddr5 rcd01

Pull Request - State: closed - Opened by mczyz-antmicro almost 2 years ago

#322 - Make tests safe to run in parallel

Pull Request - State: closed - Opened by michalsieron almost 2 years ago - 1 comment

#321 - frontend/bist: replicate LFSR output to fill the DRAM port

Pull Request - State: closed - Opened by michalsieron almost 2 years ago - 7 comments

#320 - init: Define `SDRAM_PHY_[DDR3|DDR4|...]` and `SDRAM_PHY_SUPPORTED_MEMORY`

Pull Request - State: closed - Opened by michalsieron almost 2 years ago - 2 comments

#319 - frontend/bist: properly signal finished writes

Pull Request - State: closed - Opened by michalsieron almost 2 years ago - 1 comment

#318 - DMA AXI BUG

Issue - State: closed - Opened by mohammadshahidzade almost 2 years ago - 1 comment
Labels: regression

#317 - Corresponding verilog testbench for ASIC

Issue - State: open - Opened by CarrolXC almost 2 years ago - 1 comment
Labels: question

#316 - submodules verilog

Issue - State: open - Opened by CarrolXC almost 2 years ago - 2 comments
Labels: question

#315 - sdram_init() vs. init_sequence()

Issue - State: open - Opened by epsilon537 almost 2 years ago

#314 - Fix DFITimingsChecker for DDR4 simulation

Pull Request - State: closed - Opened by michalsieron about 2 years ago - 1 comment

#313 - Add MT46H128M16 and change bankmaschine to not use A10 for col addresses.

Pull Request - State: closed - Opened by cklarhorst about 2 years ago - 1 comment

#312 - Typical litedram-L2 port sizes

Issue - State: open - Opened by bala122 about 2 years ago

#311 - Tmr bm

Pull Request - State: closed - Opened by pbrazzle about 2 years ago

#310 - Problem with adding new LPDDR module: MT46H128M16

Issue - State: closed - Opened by cklarhorst about 2 years ago - 1 comment

#309 - Simulation issue, Arty S7 (Beginner)

Issue - State: closed - Opened by TheAnimatrix about 2 years ago - 9 comments

#308 - QuarterRateGENSDRPHY

Issue - State: open - Opened by machdyne over 2 years ago - 2 comments

#307 - New to LiteDRAM

Issue - State: closed - Opened by FATHY174 over 2 years ago - 2 comments

#306 - Why are CL and CWL not included as speedgrade parameters in the module class?

Issue - State: open - Opened by jaccharrison over 2 years ago - 1 comment
Labels: enhancement, question

#305 - DDR4 Memtest Failed

Issue - State: closed - Opened by zhbeiluo over 2 years ago - 3 comments
Labels: question, bug?

#304 - Strategy steering: Best way to stream data into a custom accelerator when litedram is being used inside Litex SoC?

Issue - State: closed - Opened by francis2tm over 2 years ago - 4 comments

#303 - LiteDRAM USPDDRPHY unable to meet DDR4 timing requirements?

Issue - State: open - Opened by jaccharrison over 2 years ago - 8 comments
Labels: question, bug?

#302 - dfi: add possibility to have an external dfi injector

Pull Request - State: closed - Opened by acomodi over 2 years ago

#301 - Added AS4C4M16 for Arduino MKR Vidor 4000 support

Pull Request - State: closed - Opened by Johnsel over 2 years ago

#300 - Allow for variable DQ/DQS ratio

Pull Request - State: closed - Opened by RRozak over 2 years ago - 3 comments

#299 - ULX4M DM signal is not connected to DQS group

Issue - State: closed - Opened by goran-mahovlic over 2 years ago - 2 comments

#298 - Help creating verilog module to go from Wishbone4 to Litedram native port

Issue - State: closed - Opened by fontamsoc over 2 years ago - 1 comment

#297 - Unable to run Litedram on Digilent Genesys2

Issue - State: closed - Opened by fontamsoc over 2 years ago - 6 comments

#296 - memtest fails on arty depending on read leveling outcome

Issue - State: closed - Opened by acomodi over 2 years ago - 3 comments

#295 - s7phy: fix DDR4 mode

Pull Request - State: closed - Opened by acomodi almost 3 years ago - 2 comments

#294 - phy/s7ddrphy: Write latency calibration always.

Pull Request - State: closed - Opened by kaolpr almost 3 years ago - 1 comment

#293 - Initialization failed on Artix after e5e3b6c

Issue - State: closed - Opened by kaolpr almost 3 years ago - 5 comments

#285 - DDR3 Memory on Kintex7 325T based board randomly fails

Issue - State: closed - Opened by tongchen126 about 3 years ago - 48 comments
Labels: question, bug?

#283 - modules: add other RDIMM modules

Pull Request - State: closed - Opened by acomodi about 3 years ago - 1 comment

#281 - Help generating DDR3 Verilog module for Digilent NexysVideo Artix-7 FPGA

Issue - State: open - Opened by tambewilliam about 3 years ago - 3 comments
Labels: regression

#279 - Upconverter rewrite

Pull Request - State: open - Opened by mtdudek about 3 years ago - 4 comments