Ecosyste.ms: Issues

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GitHub / efeslab/veripass issues and pull requests

#20 - Added vcd_rebuilder and modified Makefile

Pull Request - State: closed - Opened by HieronZhang over 3 years ago

#19 - Support xilinx synthesis and depth sweep

Pull Request - State: closed - Opened by Alkaid-Benetnash over 3 years ago

#19 - Support xilinx synthesis and depth sweep

Pull Request - State: closed - Opened by Alkaid-Benetnash over 3 years ago

#18 - Pr/helper pass manualdbg

Pull Request - State: closed - Opened by HieronZhang over 3 years ago - 2 comments

#18 - Pr/helper pass manualdbg

Pull Request - State: closed - Opened by HieronZhang over 3 years ago - 2 comments

#17 - Helper pass for manual debugging

Pull Request - State: closed - Opened by Alkaid-Benetnash over 3 years ago

#17 - Helper pass for manual debugging

Pull Request - State: closed - Opened by Alkaid-Benetnash over 3 years ago

#16 - Support Xilinx ILA instrumentation in TaskSupportPass

Pull Request - State: closed - Opened by Alkaid-Benetnash over 3 years ago

#16 - Support Xilinx ILA instrumentation in TaskSupportPass

Pull Request - State: closed - Opened by Alkaid-Benetnash over 3 years ago

#15 - Add options for resource-util sweeping

Pull Request - State: closed - Opened by Alkaid-Benetnash over 3 years ago

#15 - Add options for resource-util sweeping

Pull Request - State: closed - Opened by Alkaid-Benetnash over 3 years ago

#14 - Only instrument $display with the "debug_display" verilator tag.

Pull Request - State: closed - Opened by Alkaid-Benetnash over 3 years ago - 1 comment

#14 - Only instrument $display with the "debug_display" verilator tag.

Pull Request - State: closed - Opened by Alkaid-Benetnash over 3 years ago - 1 comment

#13 - Add Logic2RegPass, which converts logic type to wire and reg

Pull Request - State: closed - Opened by Alkaid-Benetnash over 3 years ago

#13 - Add Logic2RegPass, which converts logic type to wire and reg

Pull Request - State: closed - Opened by Alkaid-Benetnash over 3 years ago

#12 - Various fixes for parsing sssp

Pull Request - State: closed - Opened by Alkaid-Benetnash over 3 years ago

#12 - Various fixes for parsing sssp

Pull Request - State: closed - Opened by Alkaid-Benetnash over 3 years ago

#11 - Various fixes for parsing sssp

Pull Request - State: closed - Opened by Alkaid-Benetnash over 3 years ago

#11 - Various fixes for parsing sssp

Pull Request - State: closed - Opened by Alkaid-Benetnash over 3 years ago

#8 - Support wire[base+const:base] type of Partselect

Pull Request - State: closed - Opened by Alkaid-Benetnash over 3 years ago

#8 - Support wire[base+const:base] type of Partselect

Pull Request - State: closed - Opened by Alkaid-Benetnash over 3 years ago

#7 - Handle qaurtus specific metacomments

Pull Request - State: closed - Opened by Alkaid-Benetnash over 3 years ago - 1 comment

#6 - Add a pass to optimize single bit operations.

Pull Request - State: closed - Opened by mjc0608 over 3 years ago

#5 - Instrument display args recording using Intel SignalTapII

Pull Request - State: closed - Opened by Alkaid-Benetnash over 3 years ago

#3 - Tracking $display args

Pull Request - State: closed - Opened by Alkaid-Benetnash over 3 years ago - 1 comment

#2 - Promote partial bit selection to intermediate wires (and assigns)

Pull Request - State: closed - Opened by Alkaid-Benetnash over 3 years ago - 2 comments

#1 - Make `gephistreamer` an optional depedendency (no runtime error)

Pull Request - State: closed - Opened by Alkaid-Benetnash over 3 years ago