Ecosyste.ms: Issues

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GitHub / efeslab/aws-fpga issues and pull requests

#13 - huge page allocation functions

Pull Request - State: closed - Opened by mjc0608 about 3 years ago - 1 comment

#12 - remove leftover bits

Pull Request - State: closed - Opened by mjc0608 about 3 years ago - 1 comment

#11 - Use almfull and ready signals in replay test

Pull Request - State: closed - Opened by mjc0608 about 3 years ago - 2 comments

#10 - Add register to read_balance

Pull Request - State: closed - Opened by mjc0608 about 3 years ago

#9 - Add alignment support for channel packing

Pull Request - State: open - Opened by mjc0608 about 3 years ago

#8 - packet length alignment and length in header

Pull Request - State: closed - Opened by mjc0608 about 3 years ago

#7 - Force packets to be 8-bit aligned

Pull Request - State: closed - Opened by mjc0608 about 3 years ago - 1 comment

#6 - Update testbench for writeback/readback , add counter for recorded bits, and fix bugs

Pull Request - State: closed - Opened by mjc0608 about 3 years ago - 1 comment

#5 - Read back replay trace

Pull Request - State: closed - Opened by mjc0608 about 3 years ago - 1 comment

#4 - add config bus

Pull Request - State: closed - Opened by mjc0608 about 3 years ago

#3 - Fix leftover_size bug and handle the finish signal

Pull Request - State: closed - Opened by mjc0608 about 3 years ago

#2 - Add write back module

Pull Request - State: closed - Opened by mjc0608 about 3 years ago

#1 - [WIP] The log writeback module (logging => PCIe mstr AXI)

Pull Request - State: closed - Opened by mjc0608 over 3 years ago - 1 comment